Memory Interface Clock Division for Multi-NAND Throughput
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Data throughput bottlenecks occur in computing systems due to data processed rates exceeding the data bandwidth or communication speed of interfaces connected to non-volatile memory devices, degrading system performance.
Innovation Solution
A memory system with a memory controller and interface circuit that divides a first clock into multiple clocks based on the number of non-volatile memories, allowing data exchange at a stable maximum operating frequency, and includes a divider, serializer, and buffer registers to synchronize and combine read data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data processing speed is increased to meet higher throughput demands, then productivity improves, but the interface communication speed becomes a bottleneck causing data loss and system performance degradation
Solution Approach 1:
The interface circuit is divided into multiple independent interface circuits, each handling a portion of the data traffic. This segmentation allows parallel data transmission paths, effectively increasing the aggregate communication bandwidth between the memory controller and memory devices without requiring a single high-speed interface that would become a bottleneck.
Solution Approach 2:
The patent transitions from a single-dimensional serial communication approach to a multi-dimensional parallel communication architecture. By introducing multiple interface circuits operating simultaneously, the system adds spatial dimensionality to data transmission, thereby scaling throughput capacity beyond the limitations of a single interface channel.
2Productivity
If multiple interface circuits are used to increase data throughput, then productivity improves, but device complexity increases due to multiple clocks and synchronization requirements
Solution Approach 1:
Multiple interface circuits are merged under a unified clock management architecture. A single master clock signal is distributed to all interface circuits, and a central synchronization mechanism coordinates their operations. This merging approach allows parallel operation of multiple interfaces while maintaining systematic control and avoiding the complexity of completely independent clock systems.
Solution Approach 2:
The clock distribution and synchronization mechanism is designed as a universal system that serves all interface circuits simultaneously. This multi-functional approach allows the same clock management infrastructure to control multiple interfaces, reducing overall system complexity compared to having dedicated clock systems for each interface.
Data Source
AI summary
A memory system includes a memory device including a plurality of non-volatile memories and an interface circuit connected to each of the plurality of non-volatile memories, and a memory controller connected to the interface circuit and configured to transmit/receive data according to a first clock, wherein the interface circuit is configured to divide the first clock into a second clock, according to the number of the plurality of non-volatile memories, and transmit/receive data to/from each of the plurality of non-volatile memories, according to the second clock.