Memory Interface Clock Gating for Synchronous Multi-Controller Access

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Solution Overview

Problem

Configurable logic integrated circuits face challenges in achieving high-speed memory accesses due to asynchronous register accesses, which can cause memory controller circuits to go out of synchronization, limiting flexibility and modularity, especially when supporting high-speed memory interface standards like DDR5.

Innovation Solution

Implementing a memory interface circuit with multiple memory controller circuits operating in synchronization, using asynchronous logic ports and a handshake protocol with gating logic circuits to ensure synchronous operation, allowing a selectable number of memory controller circuits with asynchronous logic ports to operate in lockstep for high-speed memory accesses.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If asynchronous register accesses are used in memory controller circuits, then flexibility and modularity are improved, but memory controller circuits go out of synchronization and high-speed memory accesses are limited

Engineering Contradiction:

Improveflexibility and modularityVSAvoidsynchronization

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The memory interface circuit is divided into multiple independent memory controller circuits, each capable of asynchronous register accesses for flexibility, while the overall system maintains synchronization through coordinated operation. This segmentation allows each controller to operate independently with asynchronous accesses while preserving system-wide synchronization.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A handshake protocol acts as an intermediary mechanism between memory controller circuits, enabling asynchronous register accesses to be coordinated. The handshake protocol mediates the interaction between controllers, ensuring that flexibility from asynchronous accesses does not compromise system synchronization.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If asynchronous register accesses are used, then design flexibility is improved, but memory access speed deteriorates

Engineering Contradiction:

Improvedesign flexibilityVSAvoidmemory access speed

Core Design Contradiction:

Adaptability or versatilityVSSpeed

Solution Approach 1:

The memory controller circuits dynamically switch between asynchronous and synchronous operation modes. During calibration and configuration phases, asynchronous accesses provide flexibility, while during high-speed data transfer phases, synchronous operation maximizes memory access speed. This dynamic adaptation resolves the contradiction between flexibility and speed.

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The system employs periodic calibration sequences interspersed with high-speed data transfers. During calibration periods, asynchronous register accesses occur for flexibility, while during data transfer periods, synchronous operation provides high-speed access. This periodic alternation maintains both design flexibility and high-speed performance.

Inventive Principle:

Principle #19Periodic action

3Speed

If synchronous operation is enforced, then memory access speed is improved, but flexibility and modularity deteriorate

Engineering Contradiction:

Improvememory access speedVSAvoidflexibility and modularity

Core Design Contradiction:

SpeedVSAdaptability or versatility

Solution Approach 1:

Each memory controller circuit is segmented as an independent module capable of both asynchronous and synchronous operation. This modular segmentation allows individual controllers to use asynchronous accesses for flexible configuration while participating in synchronous high-speed data transfers, preserving both flexibility and speed at different operational levels.

Inventive Principle:

Principle #1Segmentation

4Adaptability or versatility

If multiple memory controller circuits operate asynchronously, then design modularity is improved, but synchronization is lost

Engineering Contradiction:

Improvedesign modularityVSAvoidsynchronization

Core Design Contradiction:

Adaptability or versatilityVSStability of the object's composition

Solution Approach 1:

A handshake protocol implements feedback mechanisms between memory controller circuits, allowing each controller to independently perform asynchronous register accesses while receiving feedback that coordinates their operation. This feedback ensures that modular, asynchronous controllers maintain system-wide synchronization during high-speed data transfers.

Inventive Principle:

Principle #23Feedback

Data Source

PatentUS20230118912A1Techniques For Synchronous Accesses To Storage Circuits

Publication Date: 2023.04.20 ALTERA CORP

AI summary

A memory interface circuit includes first and second memory controller circuits that asynchronously receive requests for memory accesses to first and second storage circuits. The memory interface circuit also includes first and second clock gate circuits that disable and then reenable first and second clock signals in response to a clock enable signal. The first and the second memory controller circuits perform the memory accesses to the first and the second storage circuits synchronously in response to the first and the second clock signals that have been reenabled by the first and the second clock gate circuits.