Memory Card Interface Clock Recovery Without Handshake Latency
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Solution Overview
Problem
Existing interface systems for memory cards, such as those following UHS-II/-III standards, face challenges in stabilizing the inner clock frequency quickly after a dormant state, leading to increased latency and power consumption due to the need for handshake checks and continuous operation of PLL circuits during power saving modes.
Innovation Solution
The proposed interface system introduces a mode where the supply of the reference clock is stopped during a dormant state, and omits the handshake check when transitioning back to an active state, utilizing a control voltage memory unit to rapidly lock the PLL and CDR circuits, thereby reducing standby power and enabling quick recovery.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Stability of the object's composition
If the reference clock is continuously supplied during dormant state to maintain PLL operation, then clock stability is improved, but standby power consumption increases
Solution Approach 1:
The patent implements periodic action by stopping the reference clock supply during dormant state and resuming it upon activation. The PLL circuit is configured to operate only when needed (during active data transmission), rather than continuously. This periodic operation mode allows the system to maintain clock stability when required while dramatically reducing power consumption during dormant periods, directly resolving the contradiction between clock stability and standby power consumption.
2Reliability
If handshake checks are performed during state transition, then synchronization reliability is improved, but recovery latency increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring the PLL circuit with specific parameters (such as division ratios and frequency settings) before state transition occurs. When transitioning from dormant to active state, the pre-configured PLL can immediately lock onto the reference clock without requiring time-consuming handshake checks or parameter negotiations. This preliminary configuration ensures synchronization reliability is maintained while significantly reducing the recovery latency during state transitions.
3Stability of the object's composition
If PLL circuit operates continuously to maintain clock frequency, then frequency stability is improved, but power consumption increases
Solution Approach 1:
The patent implements dynamics by making the PLL circuit's operational state changeable - it can switch between active and dormant states based on data transmission requirements. The system dynamically adjusts the PLL's operation: fully operational during active state for frequency stability, and completely stopped during dormant state for power savings. This dynamic state transition capability resolves the contradiction by allowing the system to optimize between frequency stability and power consumption based on real-time needs.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach minimizes standby power consumption and allows for rapid recovery from a dormant state to an active state without the need for lengthy handshake checks, thereby reducing latency and improving overall system efficiency.
Implementation Method 1
a voltage controlled oscillator (VCO) and configured to generate an inner clock on the basis of the control voltage
Implementation Method 2
a phase-locked loop (PLL) circuit and configured to generate a control voltage on the basis of a phase difference between a reference clock and an input clock
Data Source
AI summary
According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.