External Memory Interface Clock Synchronization With Phase Compensation FIFO
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Solution Overview
Problem
Current clocking systems for system-on-chip designs face challenges in achieving single clock synchronization across independent intellectual property blocks, particularly in signal integrity and power distribution, and are limited by the use of full-rate clocks and free-running phase compensation FIFOs, which require additional logic and queues for backpressure handling.
Innovation Solution
A configurable clocking system that groups phase locked loops of each intellectual property module into a single synchronous clock using a configurable reference clock source, with sub-module clocking components for different operating frequencies, and employs phase compensation FIFOs with clock phase alignment for synchronous data transfer, supporting half-rate clocks and lower power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If full-rate clocks are used to generate DDR transfers, then data transfer speed is improved, but power consumption increases
Solution Approach 1:
The patent employs periodic action by using phase compensation FIFOs that operate in a stop-start manner rather than continuously. The FIFOs are enabled only during actual data transfer periods and disabled during idle periods, reducing power consumption while maintaining high data transfer speeds when needed. This is achieved through the periodic enabling and disabling of clocking to the FIFO structures based on backpressure conditions.
2Adaptability or versatility
If free-running phase compensation FIFOs are used, then data transfer flexibility is improved, but device complexity increases due to additional logic and queues
Solution Approach 1:
The patent extracts the backpressure handling logic from the main data path by using separate control signals (enable, clear, write pointer, read pointer) that are generated independently based on FIFO depth monitoring. This separation allows the phase compensation FIFOs to handle variable data rates and backpressure conditions without adding complex logic to the critical data transfer path, thus maintaining flexibility while reducing overall device complexity.
3Adaptability or versatility
If multiple independent clock domains are used for different IP blocks, then operational flexibility is improved, but clock synchronization difficulty increases
Solution Approach 1:
The patent merges multiple independent clock domains into a unified synchronous system by using a single system clock that is distributed to all IP blocks. Phase compensation FIFOs are placed at the interfaces between different clock domains to absorb timing variations and frequency differences, allowing each IP block to operate independently while maintaining overall system synchronization. This combining approach reduces clock synchronization complexity while preserving operational flexibility.
4Reliability
If additional logic and queues are added for backpressure handling, then data transfer reliability is improved, but device complexity increases
Solution Approach 1:
The patent introduces phase compensation FIFOs as intermediary buffers between the host interface and the memory interface. These FIFOs act as mediators that absorb backpressure by storing data temporarily when the memory interface cannot keep up with the host interface. The FIFOs include depth monitoring logic that generates control signals to prevent overflow and underflow, ensuring reliable data transfer without requiring complex backpressure handling logic in the main data path.
Data Source
AI summary
A device and method of clock synchronization for external memory interface. The device, and method, generating a clock output from a phase lock loop block via a sub-module clocking component; multiplexing the clock output through a global clock into different clock domains; clocking the data and an address or a command path by each clock domain; clocking the phase compensation FIFO by clock domain and clock phase alignment clock; generating the pointer for the phase compensation FIFO from central pointer generator block; and synchronizing the pointer of the adjacent intellectual property module with a parent intellectual property module.