Memory Interface Segmentation for Concurrent Command and Data Bursts
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Solution Overview
Problem
Existing memory sub-system interfaces process memory device commands and data bursts serially, preventing concurrent processing and leading to delayed execution in multi-plane memory devices due to shared bus usage.
Innovation Solution
Implementing a memory device interface with dedicated portions for command processing and data bursts, allowing parallel processing of commands and data bursts through independent command and data burst interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If a shared bus is used for both command and data burst processing, then device complexity is reduced, but processing speed decreases due to serial operation
Solution Approach 1:
The memory device interface is segmented into separate command interface and data burst interface portions, allowing independent parallel processing paths. This segmentation enables commands and data bursts to be processed simultaneously without interfering with each other, thereby increasing overall processing speed while maintaining manageable interface complexity through modular design.
Solution Approach 2:
The interface architecture transitions from a single-dimensional shared bus to a multi-dimensional structure with separate command and data burst processing paths. This dimensional expansion allows concurrent operations in different processing dimensions, effectively increasing throughput without proportionally increasing overall interface complexity.
2Productivity
If commands and data bursts are processed serially on a shared bus, then interface structure is simplified, but productivity decreases due to delayed execution
Solution Approach 1:
By segmenting the interface into dedicated command processing and data burst processing portions, the system enables parallel execution of memory access operations. This segmentation directly improves productivity by eliminating serial processing bottlenecks, allowing multiple operations to proceed simultaneously across different interface segments.
3Loss of time
If a shared bus is used for command and data burst processing, then manufacturing precision requirements are reduced, but loss of time increases due to sequential processing
Solution Approach 1:
The interface architecture is divided into separate command and data burst processing segments that operate in parallel. This segmentation eliminates the time loss inherent in sequential processing on shared buses, as commands and data bursts can be handled simultaneously through their respective dedicated paths without waiting for each other.
Data Source
AI summary
A first command associated with a first memory die is communicated via a first portion of an interface of the memory sub-system. A second command associated with a second memory die is communicated via the first portion of the interface to a second memory die. A data burst corresponding to the first memory die is caused to be communicated via a second portion of the interface, where the second command is communicated via the first portion of the interface concurrently with the data burst communicated via the second portion of the interface.