Memory Interface Data Scrambling for DRAM Jitter
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Solution Overview
Problem
High-speed DRAM memory devices are prone to errors due to data-dependent jitter, which can lead to repeated errors during replay operations, resulting in reduced performance, increased latency, or system failure, as conventional error correction techniques are ineffective in addressing these issues.
Innovation Solution
The implementation of synchronized data scrambling and descrambling techniques between the memory device and controller, where the memory device and controller generate and use predictable sequence values to change the scrambling pattern during replay operations, ensuring that the same pathological data pattern is not repeated, thereby reducing the likelihood of error recurrence.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If replay operations are performed to correct bit errors, then error detection capability is improved, but data-dependent jitter causes repeated errors that reduce effectiveness
Solution Approach 1:
The patent applies dynamics by making the scrambling pattern variable rather than static. The scrambler uses different seed values for different replay operations, causing the scrambling pattern to change dynamically. This prevents data-dependent jitter from causing repeated errors on the same data patterns, while still allowing error detection and correction to function effectively.
Solution Approach 2:
The patent changes the parameter of the scrambling seed value to resolve the contradiction. By varying the seed value between replay operations, the scrambling pattern changes, which prevents pathological data patterns from recurring and causing repeated errors. This maintains reliability while preserving productivity.
2Reliability
If synchronized data scrambling with changing patterns is implemented, then error recurrence is reduced, but system complexity increases
Solution Approach 1:
The patent uses feedback by having the memory controller track which operations have been performed and provide this information back to the memory device. This feedback mechanism allows both sides to synchronize their scrambling patterns without requiring complex bidirectional communication, reducing the overall system complexity while maintaining reliability.
Solution Approach 2:
The patent applies self-service by designing the scrambling mechanism where each side (memory controller and memory device) generates its own scrambling pattern independently using predetermined algorithms and seed values. This eliminates the need for complex real-time coordination and reduces system complexity while ensuring synchronization.
Data Source
AI summary
Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.