Memory Interface Duty Cycle Monitoring Using Delayed Clock Signals
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Solution Overview
Problem
Current duty cycle monitoring technologies for memory interfaces require adjustments through a duty cycle adjustment circuit, making it difficult to determine if the duty cycle falls out of specifications in the background.
Innovation Solution
A duty cycle monitoring method that involves receiving a clock signal, generating first and second delay time offsets, and outputting delayed signals to monitor whether the duty cycle conforms to a specification, using a digital element-based approach.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty cycle adjustment circuit is used to monitor duty cycle, then duty cycle can be monitored, but the system complexity increases and real-time adjustment is required
Solution Approach 1:
The patent extracts the duty cycle monitoring function from the complex adjustment circuit and implements it using simple digital elements (flip-flops, delay elements, and logic gates). The monitoring is achieved by comparing the duty cycle signal with reference signals generated by the delay elements, eliminating the need for complex continuous adjustment circuits while maintaining monitoring accuracy.
Solution Approach 2:
The patent replaces the traditional analog duty cycle adjustment circuit with a digital implementation using discrete digital elements. Instead of using continuous analog adjustment mechanisms, the invention uses digital delay elements and logic gates to generate reference signals and perform comparisons, thereby reducing system complexity while maintaining monitoring functionality.
2Measurement precision
If duty cycle adjustment circuit is used, then duty cycle monitoring is possible, but background monitoring during memory interface use becomes difficult
Solution Approach 1:
The patent implements a self-service monitoring mechanism where the digital elements continuously generate reference signals and perform duty cycle comparisons automatically during normal memory interface operation. The monitoring circuit uses the existing clock signals and generates internal reference signals through delay elements, enabling autonomous background monitoring without requiring external intervention or system suspension.
Solution Approach 2:
The monitoring function operates continuously during normal memory interface usage by utilizing the ongoing clock signals. The digital elements continuously generate reference signals and perform comparisons, ensuring uninterrupted duty cycle monitoring throughout the operational period without requiring system pauses or additional adjustment phases.
3Reliability
If traditional duty cycle monitoring is implemented, then monitoring function is achieved, but real-time adjustments are required which complicates the system
Solution Approach 1:
The patent pre-generates reference signals with known duty cycle characteristics using delay elements before comparison with the actual duty cycle signal. By preparing these reference signals in advance through simple delay circuits, the system establishes a baseline for comparison that simplifies the monitoring process and eliminates the need for complex real-time adjustment mechanisms while ensuring specification compliance.
Data Source
AI summary
Disclosed herein are a duty cycle monitoring method and apparatus for a memory interface, including receiving a clock signal as input and generating a first delay time offset and a second delay time offset, receiving the clock signal and the first delay time offset and then outputting a first delayed signal, receiving the first delayed signal and the second delay time offset and then outputting a second delayed signal, receiving the clock signal and the second delayed signal and then outputting a delay value corresponding to a half-period of the clock signal, and monitoring, based on the first delayed signal, whether a duty cycle of the clock signal conforms to a duty cycle specification.