Memory Interface Deskewing via Clock Phase Advancement
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Solution Overview
Problem
In high-speed memory interfaces with multiple data lanes, process variations during fabrication cause clock signal delays, leading to lane-to-lane skew and synchronization issues between memory devices and the memory controller, resulting in desynchronization of data read and transmitted back to the controller.
Innovation Solution
The memory controller advances the phase of the system clock signal forwarded to slower memory devices by an amount corresponding to the skew, ensuring that state machines in these devices operate earlier, thus eliminating skew by synchronizing data read from all memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the system clock signal is forwarded to multiple memory devices, then the memory devices can be synchronized to the same system clock signal, but process variations cause different propagation delays resulting in lane-to-lane skew
Solution Approach 1:
The patent applies preliminary action by measuring the lane-to-lane skew between clock signals before normal operation, and pre-calculating the phase adjustment amounts needed for each memory device. This allows the system to compensate for process variations in advance, ensuring synchronized operation without requiring hardware changes or increasing complexity.
2Manufacturing precision
If conventional deskewing techniques are used with synchronization latches, then small lane-to-lane skew can be corrected, but large skew in high-speed interfaces exceeds the correction capability
Solution Approach 1:
The patent changes the parameter of clock signal phase by dynamically adjusting the phase of forwarded clock signals to each memory device based on measured skew. This phase adjustment allows the system to correct large lane-to-lane skew in high-speed interfaces (e.g., 2.15 GHz operating at 4.3 Gbps DDR signaling) without relying on synchronization latches that only work for small skew amounts.
3Ease of operation
If the phase of parallel clocks in memory controller PHY varies from lane to lane, then each lane can be synchronized to its bit stream timing, but lane-to-lane skew of bit streams must be controlled
Solution Approach 1:
The patent implements feedback by measuring the actual lane-to-lane skew between clock signals arriving at different memory devices, using this measurement to determine the required phase adjustment for each device's clock signal. This closed-loop approach ensures that bit stream skew is controlled while allowing each lane's parallel clock to be optimally synchronized to its specific bit stream timing.
Data Source
AI summary
In a memory system in which a system clock signal is forwarded from the memory controller to multiple memory devices, the phase of the system clock signal forwarded to the slower memory device is advanced relative to the system clock signal forwarded to the faster memory device by a phase corresponding to the skew on the data links corresponding to the memory devices. This causes the state machine of the slower memory device to change states and advance earlier than the state machine in the faster memory device, and as a result, the data read from both the slower memory device and the faster memory device are unskewed on the data links between the memory controller and the memory devices.