Memory Interface Device for DRAM Weak Cell Remapping
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Solution Overview
Problem
As DRAM memory cells shrink due to advancements in process technology, they become more susceptible to errors from aging and repeated accesses, leading to increased weak bits that cannot be adequately corrected by conventional methods, which affects data retention time and memory performance.
Innovation Solution
Implementing a memory interface device with an Address Match Table and a programmable test sequencer that identifies and dynamically replaces faulty or weak memory cells with spare cells, ensuring continuous data integrity and extended memory performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If DRAM memory cells are shrunk to increase memory capacity, then memory capacity is improved, but data retention time deteriorates due to increased leakage and reduced storage capacitance
Solution Approach 1:
The patent implements preliminary action by performing memory testing and identifying weak cells during the manufacturing process before the memory device is deployed. The memory controller is pre-configured with information about defective cells, allowing it to proactively remap these cells to spare locations before they can cause operational failures. This preventive approach ensures that cells with potentially problematic data retention characteristics are addressed before they degrade during normal operation.
Solution Approach 2:
The patent applies parameter changes by dynamically altering the mapping parameters between logical addresses and physical memory cell locations. When a weak cell is detected or anticipated to fail, the system changes the address mapping parameters to redirect accesses away from problematic cells to functional spare cells. This allows the memory system to adapt its physical configuration in response to the deteriorating data retention characteristics of shrunk memory cells.
2Quantity of substance
If access transistor size is reduced to increase memory density, then memory density is improved, but leakage increases which reduces data retention time
Solution Approach 1:
The patent extracts and isolates the problematic leakage issue by identifying individual cells that exhibit excessive leakage characteristics. Rather than attempting to fix the leakage in the shrunk transistors themselves, the system extracts these defective cells from the active memory space and relocates their data to spare cells with acceptable leakage characteristics. This separation allows the high-density shrunk transistor array to maintain its density advantage while the leakage problem is handled through selective removal and remapping.
Solution Approach 2:
The patent performs preliminary identification and characterization of cells with high leakage characteristics during manufacturing testing. By detecting and flagging these cells before deployment, the system can pre-configure remapping tables that redirect accesses away from high-leakage cells. This preliminary action prevents energy loss from excessive leakage before it occurs during normal operation, allowing the system to maintain high density with shrunk transistors while compensating for their leakage weaknesses.
3Quantity of substance
If storage capacitor size is reduced to increase memory capacity, then memory capacity is improved, but storage capacitance decreases which adversely affects data retention time
Solution Approach 1:
The patent implements preliminary characterization of storage capacitor performance during manufacturing, identifying cells with reduced capacitance values that may lead to poor data retention. By detecting these cells early and mapping them to spare locations with adequate capacitance, the system ensures that cells with insufficient storage capability are replaced before they can cause data loss during operation. This allows the memory device to achieve high capacity with small capacitors while maintaining reliability through pre-screening and remapping.
Solution Approach 2:
The patent changes the operational parameters of the memory system by dynamically adjusting the mapping between logical addresses and physical cell locations based on measured capacitance values. Cells with lower-than-desired capacitance are assigned different physical locations in the remapped configuration, effectively changing which cells are used for data storage. This parameter change allows the system to maintain high memory capacity with reduced capacitor sizes while ensuring that only cells with adequate retention characteristics are used for actual data storage.
Data Source
AI summary
An interface device for a memory module comprising a plurality of DRAMs includes a memory configured to store DRAM test program instructions, and a programmable processing device coupled to the memory, wherein the programmable processing device is configured to receive input data and input memory addresses from an external processor, wherein the programmable processing device is configured to provide data and memory addresses to the plurality of DRAMs, and wherein the programmable processing device is programmed to perform operations specified by the DRAM test program instructions.