Shared Memory Interface DLL for SDRAM Power Reduction
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Solution Overview
Problem
Synchronous memory systems face high power consumption due to the presence of multiple Delay Locked Loop (DLL) and voltage generator circuits in SDRAM components, which are replicated across many memory components, leading to significant overall power usage in systems like portable devices.
Innovation Solution
A common DLL circuit and/or voltage generator circuit is provided in the memory interface, with corresponding circuits in SDRAM components disabled or bypassed, allowing these resources to be shared across all components, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If DLL and voltage generator circuits are included in each SDRAM component, then each component can operate independently, but power consumption increases significantly
Solution Approach 1:
The patent merges the DLL and voltage generator circuits from individual SDRAM components into a shared memory interface unit. This consolidation allows multiple SDRAM components to share common DLL circuitry and voltage generation resources, eliminating redundant power consumption while maintaining independent operation capability through the shared interface.
Solution Approach 2:
The memory interface is designed with universal DLL and voltage generator circuits that serve multiple SDRAM components simultaneously. This multi-functional approach allows a single set of circuits to support numerous memory components, reducing overall power consumption while maintaining system reliability and independent access to each component.
2Adaptability or versatility
If DLL and voltage generator circuits are replicated in each SDRAM component, then each component has full functionality, but manufacturing costs increase
Solution Approach 1:
By consolidating DLL and voltage generator circuits into the memory interface rather than replicating them in each SDRAM component, the patent reduces the bill of materials and manufacturing complexity. This merging approach maintains full functionality through the shared interface while lowering per-system manufacturing costs.
3Ease of operation
If multiple DLL circuits are present in SDRAM components, then each component can be accessed independently, but the system becomes more complex
Solution Approach 1:
The memory interface acts as an intermediary between the memory controller and SDRAM components, centralizing the DLL and voltage generator circuits. This intermediary approach maintains independent access capability to each SDRAM component while reducing system complexity by eliminating redundant circuits through the shared interface architecture.
Data Source
AI summary
A common Delay Locked Loop (DLL) circuit and/or voltage generator circuit is provided in, or associated with. a memory interface interposed between a memory controller and a plurality of memory components. Corresponding circuits in the memory components are disabled and/or bypassed, or the memory components are manufactured without the circuits. Both the DLL circuit and voltage generator draw current, which is multiplied by the number of memory components in a memory system. By operating a single DLL circuit and/or voltage generator in or associated with the memory interface, that generates a read clock signal and/or various voltage levels, respectively, for all memory components in the memory system, power consumption may be significantly reduced.