Memory Interface DQS Signal Cleaning via Dynamic Offset

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Solution Overview

Problem

Existing memory interface devices generate unwanted pulses when restoring high-speed data strobe signals, particularly during transitions to high impedance states, requiring complex circuitry and additional correction mechanisms to prevent errors.

Innovation Solution

A memory interface device with a DQS input buffer, offset control circuit, and duty adjustment buffer that uses static and dynamic offsets to clean data strobe signals, eliminating the need for separate gate signals or training, thereby simplifying the circuit and reducing area and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If a CTLE is used to restore high-speed signals, then high-frequency components are recovered, but unwanted high-frequency signals and pulses are generated

Engineering Contradiction:
Improvesignal recovery accuracyVSAvoidunwanted pulses
Core Design Contradiction:
Measurement precisionVSObject-generated harmful factors

Solution Approach 1:

The patent converts the harmful unwanted high-frequency pulses generated by CTLE into beneficial signal cleaning by using the same CTLE circuit to detect and eliminate these pulses through a cleaning signal generation mechanism that removes the harmful components while preserving the useful data signal

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Solution Approach 2:

The patent introduces an intermediary cleaning signal generation circuit that mediates between the CTLE output and the final signal, using this intermediate stage to filter out unwanted pulses before the signal reaches subsequent processing stages

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If additional correction mechanisms are added to prevent unwanted pulses, then signal accuracy is improved, but device complexity increases

Engineering Contradiction:
Improvesignal integrityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the signal restoration function and the unwanted pulse cleaning function into a single integrated circuit block, combining what would traditionally be separate correction mechanisms into one unified structure that performs both functions simultaneously

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a multi-functional circuit block that simultaneously performs signal amplification, high-frequency component recovery, and unwanted pulse elimination, allowing a single circuit to execute multiple functions that would otherwise require separate dedicated circuits

Inventive Principle:
Principle #6Universality (Multi-functionality)

3Object-generated harmful factors

If separate gate signals or DQS training are used for DQS cleaning, then unwanted pulses are removed, but area and power consumption increase

Engineering Contradiction:
Improveunwanted pulsesVSAvoidpower consumption
Core Design Contradiction:
Object-generated harmful factorsVSUse of energy by moving object

Solution Approach 1:

The patent implements a self-service mechanism where the circuit automatically generates cleaning signals based on its own output signals, eliminating the need for external gate signals or separate training sequences, thereby reducing power consumption and area while maintaining the ability to remove unwanted pulses

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12087392B2Memory interface device
Publication Date: 2024.09.10 ELECTRONICS & TELECOMM RES INST
  • US12087392B2 patent drawing
  • US12087392B2 patent drawing
  • US12087392B2 patent drawing

AI summary

Provided is a memory interface device. A memory interface device, comprising: a DQS input buffer configured to receive input data strobe signals and output a first intermediate data strobe signal, the DQS input buffer providing a static offset; an offset control circuit configured to receive the first intermediate data strobe signal and output a second intermediate data strobe signal; and a duty adjustment buffer configured to receive the second intermediate data strobe signal and output a clean data strobe signal, wherein the offset control circuit provides a dynamic offset using the clean data strobe signal.