Memory Interface Duty Cycle Correction via Blocking and Unblocking
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Solution Overview
Problem
Existing memory systems face challenges in accurately correcting the duty cycle of clock signals, leading to inefficiencies and potential errors in data transfer, particularly at high speeds, due to limitations in duty cycle correction methods that are often incomplete or inaccurate.
Innovation Solution
A memory system and method that include a controller and an interface device with a signal control mechanism, utilizing blocking, correction, and unblocking commands to deactivate and reactivate the internal channel for precise duty cycle correction based on measured clock cycle times, ensuring accurate data transfer by adjusting the duty cycle to approximately 50%.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If duty cycle correction is performed continuously during data transfer, then data transfer speed is maintained, but correction accuracy deteriorates due to incomplete correction
Solution Approach 1:
The patent applies preliminary action by performing duty cycle correction in advance during a dedicated period before normal data transfer begins. The interface device measures the actual clock cycle time and calculates the required duty cycle adjustment, then applies the correction before resuming data transfer operations. This ensures accurate correction without interfering with ongoing data transfer performance.
Solution Approach 2:
The patent implements periodic action by establishing a dedicated correction period that occurs periodically or initially before data transfer. During this specific time window, the interface device performs duty cycle measurement and correction calculations, then suspends correction operations during active data transfer. This periodic approach allows accurate correction while maintaining continuous data transfer capability.
2Measurement precision
If the internal channel is always active for data transfer, then data transfer efficiency is maximized, but duty cycle correction cannot be accurately performed
Solution Approach 1:
The patent performs duty cycle measurement and correction calculations during a preliminary period when the internal channel is temporarily suspended for correction operations. Once the correction is complete, the channel is reactivated for data transfer. This preliminary action ensures accurate measurement without compromising subsequent transfer efficiency.
Solution Approach 2:
The patent introduces an intermediary correction period that acts as a mediator between the need for accurate duty cycle correction and continuous data transfer operation. During this intermediary period, the internal channel is temporarily deactivated to allow precise measurement, then reactivated for efficient data transfer. This intermediary mechanism resolves the conflict between accuracy and efficiency.
3Extent of automation
If duty cycle correction is performed during data transfer operations, then correction can be applied in real-time, but data transfer reliability deteriorates due to potential errors
Solution Approach 1:
The patent applies preliminary action by completing all duty cycle correction calculations and adjustments before resuming data transfer operations. The interface device measures clock cycle time, calculates the required duty cycle adjustment, and applies the correction in advance, ensuring that data transfer begins with already-corrected timing parameters. This eliminates the risk of errors during simultaneous operation.
Solution Approach 2:
The patent implements a brief suspension period during correction operations, temporarily skipping data transfer to ensure complete and accurate correction. This brief interruption is followed by resuming data transfer with corrected timing parameters. The skipping approach ensures reliability by preventing concurrent operations that could introduce errors.
Data Source
AI summary
A memory system includes: a memory device suitable for storing a data; a controller suitable for controlling an operation of the memory device based on a control signal; and an interface device includes a signal transfer device suitable for transferring the control signal from the controller to the memory device and transferring the data between the memory device and the controller; and a signal control device suitable for controlling an operation of the signal transfer device in response to an interface control signal included in the control signal, wherein the interface control signal includes a blocking command for stopping an operation of the signal transfer device, a correction command for correcting a duty cycle of the control signal, and an unblocking command for resuming the operation in response to the corrected control signal, of the signal transfer device.