Memory Interface Circuit for Duty Cycle Correction Under High Loading
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Solution Overview
Problem
Existing memory systems face challenges in accurately correcting the clock signal, leading to inefficiencies and reduced performance due to Inter-Symbol Interference (ISI) and the need for duty cycle correction, particularly in high-capacity memory systems with increased loading capacitance.
Innovation Solution
The memory system incorporates an interface circuit that blocks commands between the interface circuit and semiconductor memory for internal operations like signal controlling, training, read, ZQ calibration, and driving force control, and utilizes a controller to send control signals for duty cycle correction to interface devices, improving the operation of memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory system increases its capacity, then more data can be stored, but the loading capacitance increases causing Inter-Symbol Interference and reduced clock correction accuracy
Solution Approach 1:
The interface circuit is divided into multiple internal channels (first internal channel, second internal channel, etc.), each handling specific tasks. This segmentation allows the system to manage capacitance loading more effectively while maintaining high capacity, as each channel operates independently with controlled signal paths.
Solution Approach 2:
The interface circuit acts as an intermediary between the controller and the semiconductor memory device. It performs duty cycle correction and signal conditioning, mediating the interaction to compensate for the harmful effects of increased loading capacitance in high-capacity systems.
2Measurement precision
If the interface circuit performs internal operations like duty cycle correction, then clock accuracy improves, but command transfer between interface circuit and semiconductor memory must be blocked
Solution Approach 1:
The interface circuit performs duty cycle correction and other internal operations in advance before actual data transfer begins. By preparing and adjusting clock signals beforehand, the system ensures accurate timing for subsequent command transfers without blocking them permanently.
Solution Approach 2:
The interface circuit alternates between internal operations (duty cycle correction) and command transfer operations in a periodic manner. During internal operation phases, command transfer is blocked; during transfer phases, the interface circuit communicates with the semiconductor memory. This periodic switching maintains both accuracy and productivity.
3Measurement precision
If the interface circuit blocks command transfer for internal operations, then duty cycle correction can be performed accurately, but the operation time is extended
Solution Approach 1:
Duty cycle correction is performed as a preliminary action during initialization or training phases before normal data transfer begins. This ensures that timing adjustments are made when the system is already in a controlled state, minimizing the impact on overall operation time.
Solution Approach 2:
The interface circuit maintains continuous useful action by overlapping internal operations with command transfer operations in time. During internal operation phases, the semiconductor memory can perform other tasks, and during transfer phases, the interface circuit prepares signals. This continuity reduces the total time lost to blocking.
Data Source
AI summary
A memory system includes a memory device including an interface circuit and a semiconductor memory, and a controller to generate a command for controlling the memory device. The interface circuit receives the command from the controller; determines whether the command is for the semiconductor memory or the interface circuit; and when it is determined that the command is for the interface circuit, performs a blocking operation to block transfer of the command between the interface circuit and the semiconductor memory and performs an internal operation of the interface circuit. The internal operation includes a signal controlling operation, a training operation, a read operation, an on-die termination operation, a ZQ calibration operation, or a driving force control operation.