Memory Interface Circuit Emulating Capacity Using Segmented Chips
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Solution Overview
Problem
The increasing demand for high-capacity memory modules is hindered by the exponential relationship between memory chip capacity and cost, making large capacity memory modules cost-prohibitive, and the reduction in memory module slots in systems necessitates an effective way to utilize low-cost memory chips.
Innovation Solution
A memory subsystem with an interface circuit that couples with multiple memory circuits to emulate different aspects such as signal, capacity, timing, and logical interface, effectively presenting a higher capacity or different protocol to the system, using a buffer chip to communicate signals and manage memory operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If large capacity memory modules are manufactured using high capacity memory chips, then memory capacity is improved, but cost increases exponentially
Solution Approach 1:
The invention segments a single large-capacity memory chip into multiple smaller memory circuits (e.g., four 512Mb chips to emulate one 2Gb chip). This segmentation allows the system to achieve high capacity using multiple low-cost smaller chips instead of one expensive high-capacity chip, directly resolving the cost-capacity contradiction.
Solution Approach 2:
The invention creates a virtual copy or emulation of a high-capacity memory circuit using multiple lower-capacity physical memory circuits. The interface circuit emulates the behavior, timing, and interface characteristics of a single large chip, allowing the system to utilize cheap small chips while presenting the appearance and functionality of expensive large chips to the host system.
2Volume of moving object
If the number of memory module slots is reduced to accommodate small form factor machines, then device compactness is improved, but memory expandability deteriorates
Solution Approach 1:
The interface circuit provides multi-functionality by supporting both native memory chip operations and emulated high-capacity memory operations through a single memory module slot. This allows the system to maintain compact form factor with fewer slots while achieving memory expandability through the emulation capability that can present different capacity and protocol configurations.
Solution Approach 2:
The interface circuit acts as an intermediary between the host system and multiple memory circuits. It mediates the communication, translating between the host's expectations for high-capacity memory and the actual capabilities of multiple smaller memory chips, thereby enabling memory expandability without additional physical slots.
3Ease of manufacture
If multiple memory circuits are used to emulate high capacity memory, then cost is reduced, but device complexity increases
Solution Approach 1:
The interface circuit serves as an intermediary that manages the complexity of coordinating multiple memory circuits. It handles address decoding, data multiplexing, and timing synchronization, thereby isolating the complexity from the host system while enabling cost-effective high-capacity memory implementation using multiple smaller chips.
4Quantity of substance
If high capacity memory modules are used to meet memory requirements, then memory capacity is improved, but power dissipation increases
Solution Approach 1:
The invention segments high-capacity memory into multiple smaller memory circuits, each operating at lower power levels. By using multiple 512Mb chips instead of one 2Gb chip, the system achieves the same capacity while benefiting from the lower power dissipation characteristics of smaller chips, as power consumption does not scale linearly with capacity.
Data Source
AI summary
A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.