Memory Interface Error Detection Before Data Storage

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Solution Overview

Problem

Data memory devices face errors in commands, data, and status information due to electrical noise, connection faults, and degradation over time, which can lead to data corruption and storage issues.

Innovation Solution

Incorporating an error detection component within the data memory device's interface to detect and handle errors using error control codes, such as cyclical redundancy codes, before data is stored, ensuring data integrity and reliability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If error detection component is added to the data memory device interface, then data integrity and reliability are improved, but device complexity increases

Engineering Contradiction:
Improvedata integrityVSAvoiddevice complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The error detection component performs preliminary error detection on incoming data before the data is stored in the memory array. By detecting errors in advance during the data reception phase rather than after storage, the system prevents corrupted data from being written to memory, thereby improving data integrity without requiring complex post-storage error handling mechanisms.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The error detection component acts as an intermediary between the interface and the memory array. It intercepts data flowing through the interface, performs error detection using error control codes, and only allows clean data to proceed to the memory array. This intermediary function isolates the memory array from error-prone interface operations while maintaining a relatively simple overall architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If error detection is performed on all received data, then data corruption risk is reduced, but processing time increases

Engineering Contradiction:
Improvedata corruption preventionVSAvoidprocessing time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The error detection component applies error detection codes to data at a rate that ensures complete coverage of all incoming data streams. By performing error detection on all received data without exception, the system guarantees that no corrupted data slips through to the memory array, achieving maximum data corruption prevention despite the additional processing time required.

Inventive Principle:
Principle #16Partial or excessive action

3Reliability

If error control codes are generated and processed, then error detection capability is improved, but computational overhead increases

Engineering Contradiction:
Improveerror detection capabilityVSAvoidcomputational overhead
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

The error detection component replaces complex computational error analysis with simpler error control code generation and verification. Instead of performing sophisticated algorithms to detect errors, the system uses predetermined error control codes (such as CRC codes) that can be generated and checked using standardized, computationally efficient procedures, thereby reducing overall computational overhead while maintaining strong error detection capability.

Inventive Principle:
Principle #28Mechanics substitution (Replace mechanical system)

Data Source

PatentUS10152249B2Data memory device and controller with interface error detection and handling logic
Publication Date: 2018.12.11 SEAGATE TECH LLC
  • US10152249B2 patent drawing
  • US10152249B2 patent drawing
  • US10152249B2 patent drawing

AI summary

The present disclosure provides a data storage system including a data memory device and controller having interface error detection and handling logic. In one example, a solid-state data memory device is provided and includes a semiconductor package. A memory array is provided in the semiconductor package and an interface is provided that is communicatively couplable to a device bus for receiving data to be stored to the memory array. An error detection component is provided in the semiconductor package and is associated with the interface of the solid-state data memory device. The error detection component is configured to detect errors occurring on data received at the interface prior to the data being stored to the memory array.