Memory Interface Feed Forward Training for VT Drift
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Solution Overview
Problem
Modern GDDR memory systems experience voltage and temperature (VT) drift, leading to the need for periodic retraining, which stalls system operations and affects performance, especially in graphics workloads.
Innovation Solution
A data processing system with a calibration circuit and compensation circuit that performs a link retraining sequence for DQ lanes, determines phase offsets, and applies corresponding offsets to CA lanes, reducing the need for frequent retraining by leveraging PHY circuit capabilities to adjust for VT drift without recalibration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic retraining is performed to compensate for VT drift, then reliability of data reception is improved, but productivity decreases due to system stalling
Solution Approach 1:
The patent performs link retraining on a subset of DQ lanes beforehand to determine phase offset values, which are then applied as compensation to CA lanes during normal operation. This preliminary action on DQ lanes prevents the need for disruptive full-link retraining, maintaining system productivity while ensuring reliability through pre-calculated phase offsets.
Solution Approach 2:
The patent divides the memory interface into separate DQ lanes and CA lanes, and further segments the retraining process to apply to only a subset of DQ lanes. This segmentation allows phase offset determination to be performed independently on selected lanes without stalling the entire system, resolving the contradiction between reliable data reception and continuous operation.
2Measurement precision
If full link retraining is performed on all lanes, then measurement precision of phase offset is improved, but loss of time increases due to system stalling
Solution Approach 1:
The patent applies partial action by performing link retraining on only a subset of DQ lanes rather than all lanes. The phase offset values determined from this partial training are then sufficient to compensate for VT drift across all CA lanes, achieving adequate measurement precision without the time cost of complete system retraining.
Solution Approach 2:
The phase offset values determined from training a subset of DQ lanes serve a universal function by being applied to compensate all CA lanes. This multi-functionality allows the system to achieve accurate phase offset measurement for the entire memory interface through training only part of it, reducing retraining time while maintaining precision.
3Adaptability or versatility
If high-speed link phase retraining is performed periodically, then adaptability to VT drift is improved, but productivity decreases due to operation stalls
Solution Approach 1:
The system performs preliminary link retraining on a subset of DQ lanes to determine phase offset values before normal operation begins. These pre-determined offsets are then applied to CA lanes during operation, providing adaptability to VT drift without requiring periodic stalls for retraining, thus maintaining high productivity.
Solution Approach 2:
The patent uses DQ lane training results as an intermediary to determine phase offsets that are then applied to CA lanes. This intermediary approach allows the system to adapt to VT drift through DQ lane characteristics without performing direct, disruptive retraining on the critical CA lanes, preserving system throughput while maintaining adaptability.
Data Source
AI summary
A data processor, system, method, integrated circuit are provided which update timing values for accessing a memory to compensate for voltage and temperature (VT) drift during operation. The method includes performing a link retraining sequence for a plurality of DQ lanes of the memory bus and determining a first phase offset based on the link retraining. The method includes calculating a second offset based on the first offset, applying the second offset to a plurality of command CA lanes of the memory bus.


