Glitch-Free Memory Interface Circuit Using Delayed Strobe Logic
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In double data rate systems, such as DDR-SDRAM, the interface circuit faces challenges in determining data capture timing due to varying wiring lengths between the memory and host apparatus, leading to potential malfunctions from glitch noise introduced by noise intrusion during data transfer.
Innovation Solution
The interface circuit employs a delay circuit to generate a delayed data strobe signal, which is then logically operated with the original signal to produce glitch-free strobe signals, allowing flip-flop circuits to latch data accurately, thereby preventing malfunctions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the interface circuit directly captures data based on the data strobe signal in double data rate systems, then data transfer speed is improved, but glitch noise from noise intrusion causes malfunctions due to varying wiring lengths
Solution Approach 1:
The patent applies preliminary action by generating a delayed version of the data strobe signal before the actual data capture process. The delay circuit creates a time-shifted copy of the strobe signal, which is then used in logical operations to identify and filter out glitch noise. This preliminary processing of the strobe signal allows the system to prepare clean capture timing information before data latching occurs, thus maintaining high-speed double data rate operation while preventing malfunctions from glitch noise.
Solution Approach 2:
The patent uses an intermediary approach by introducing logical operation circuits that process both the original and delayed strobe signals. These logical operations act as intermediaries between the raw strobe signal and the final data capture decision. The intermediary logical processing identifies valid edges versus glitch noise by comparing the timing relationships between original and delayed signals, thereby mediating the data capture process to ensure reliability without sacrificing speed.
2Adaptability or versatility
If the wiring length between memory and host apparatus is varied to adapt to different systems, then system adaptability is improved, but timing determination for data capture becomes difficult due to different flight times
Solution Approach 1:
The patent applies parameter changes by transforming the fixed timing assumption into a variable timing solution. Instead of assuming a fixed relationship between strobe signal and data arrival, the system uses delay circuits to create multiple time references and logical operations to dynamically determine the correct capture timing. This allows the interface to adapt to different wiring lengths and flight times while maintaining accurate data capture, thus resolving the contradiction between system adaptability and timing determination difficulty.
3Productivity
If the pulse width of data is reduced to accommodate double data rate operation, then data transfer efficiency is improved, but the interface circuit becomes more sensitive to timing variations and glitch noise
Solution Approach 1:
The patent applies preliminary action by preprocessing the strobe signal through delay circuits and logical operations before using it to trigger data capture. This preliminary processing establishes a time margin that accommodates the reduced pulse width of double data rate operation. By preparing the capture timing information in advance and filtering out potential glitches through logical comparison of delayed and original signals, the system maintains high data transfer efficiency while reducing sensitivity to timing variations and glitch noise.
Data Source
AI summary
An interface circuit includes a delay circuit that generates a delay signal obtained by delaying a data strobe signal, a first logical circuit that performs a logical operation of on the data strobe signal and the delay signal, and outputs an operation result as a first strobe signal, a second logical circuit that receives the first strobe signal and generates a second strobe signal that is complementary to the first strobe signal; a first latch circuit that latches a data signal based on the first strobe signal, and a second latch circuit that latches the data signal based on the second strobe signal.