Multi-Channel Memory Interface for Idle-Cycle Bandwidth Limits
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Solution Overview
Problem
Chiplet systems face inefficiencies in memory device utilization due to idle data cycles caused by activate-to-activate delay requirements in memory access protocols, limiting bandwidth and reducing the effective use of memory channels.
Innovation Solution
A memory controller is configured to provide independent data and command/address signals to separate sub-portions of wider industry standard memory interfaces, allowing concurrent access to independent memory arrays through multiple hardware channels, thereby optimizing memory access operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory access protocols enforce activate-to-activate delay requirements, then memory device reliability is maintained, but idle data cycles increase and bandwidth is reduced
Solution Approach 1:
The memory interface is segmented into multiple independent hardware channels (first and second channels), each capable of independent memory access operations. This segmentation allows the system to bypass activate-to-activate delay limitations by distributing access requests across multiple channels, thereby maintaining reliability while increasing overall bandwidth and reducing idle cycles.
Solution Approach 2:
The patent introduces a temporal dimension to memory access by enabling concurrent operations across multiple channels. Instead of sequential access limited by activate-to-activate delays on a single channel, the system operates in parallel time slices across multiple channels, effectively adding a dimensional aspect to memory access that increases productivity without compromising reliability.
2Device complexity
If single hardware channel is used for memory access, then device complexity is reduced, but memory device utilization efficiency decreases
Solution Approach 1:
The memory interface is divided into multiple independent hardware channels, each handling separate memory access operations. This segmentation increases device utilization by allowing parallel access to different memory regions simultaneously, while each individual channel maintains relatively simple structure, balancing complexity and productivity.
Solution Approach 2:
Each hardware channel is designed as a universal interface capable of independent memory access operations. This multi-functionality allows the same channel structure to handle various memory access patterns (reads, writes, refreshes) independently, increasing overall device utilization without proportionally increasing complexity.
Data Source
AI summary
A system including a memory controller chiplet having a memory interface that is configured to couple the memory controller chiplet to first and second memory devices. The memory interface includes first and second memory channels having respective data widths, and configured to couple first and second I/O interfaces of the memory controller chiplet to an interface of the first memory device having a data channel width at least equal to the combined first and second memory channel widths, where the first and second memory channels have independent command/address (CA) paths; and third and fourth memory channels having respective data widths, and configured to couple third and fourth I/O interfaces of the memory controller chiplet to an interface of the second memory device having a data channel width at least equal to the combined third and fourth memory channel widths, wherein the third and fourth memory channels have independent CA paths.