Memory Interface Impedance Calibration via SRAM Test Storage
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Solution Overview
Problem
High-speed DRAM bus operations lead to signaling issues due to reflections from stub lines, necessitating calibration of on-die termination (ODT) and driver impedance to ensure effective communication.
Innovation Solution
A method and apparatus for configuring impedance of memory interfaces by setting default impedance values for ODT and driver variable resistance, performing tests, and storing results in SRAM to facilitate calibration, allowing for automatic determination and programming of optimal impedance settings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If high data rate is used in DRAM bus, then data transmission speed is improved, but signaling problems occur due to reflections from stub lines
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting the impedance values of the driver and on-die termination (ODT) based on test results stored in SRAM. The system varies impedance parameters to optimize signal integrity at high data rates, resolving the contradiction between speed and reliability through adaptive parameter tuning rather than fixed settings.
Solution Approach 2:
The patent implements feedback by performing tests with multiple impedance combinations and storing results in SRAM for later retrieval during calibration. The calibration host uses this stored test data to determine optimal impedance settings, creating a feedback loop that ensures reliable signal transmission at high speeds by learning from previous test outcomes.
2Reliability
If driver and ODT impedance are calibrated to solve signaling problems, then signal integrity is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by performing impedance tests and storing results in SRAM before the actual calibration operation. This pre-computed test data is then retrieved and used during calibration, simplifying the overall process by eliminating the need for complex real-time testing during calibration operations.
Solution Approach 2:
The patent uses copying by storing test results in SRAM memory as a copy of the calibration data. This memory copy allows the calibration host to retrieve and apply optimal impedance settings without repeatedly performing complex tests, thereby reducing device complexity while maintaining calibration accuracy.
3Measurement precision
If multiple impedance combinations are tested and stored in SRAM, then calibration accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent applies dynamics by implementing variable impedance settings that can be adjusted based on test results. Rather than requiring fixed, precise manufacturing values, the system dynamically adapts impedance parameters within ranges, reducing manufacturing precision requirements while maintaining calibration accuracy through software-controlled adjustments.
Solution Approach 2:
The patent uses partial action by testing a limited number of representative impedance combinations and storing results in SRAM. This partial testing approach provides sufficient calibration data without requiring exhaustive testing of all possible combinations, thereby reducing manufacturing precision requirements while maintaining adequate calibration accuracy.
Data Source
AI summary
The invention introduces a method for configuring impedance of memory interfaces, performed by a processing unit, including: setting a first impedance value associated with an on-die termination (ODT) for a receiver of a controller to a first default value; setting a second impedance value associated with a driver variable resistance for a transmitter of a memory device to a second default value; performing tests for test combinations each comprises a third impedance value associated with a driver variable resistance for a transmitter of the controller and a fourth impedance value associated with an ODT for a receiver of the memory device; and storing a test result for each in a predefined location of a static random access memory (SRAM), thereby enabling a calibration host to obtain the test result for each from the SRAM.