Memory Interface Verification via IO Pin Voltage Control
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Solution Overview
Problem
The increased complexity of multiple die stacking in memory devices leads to manufacturing defects in interconnections, causing malfunctions in the memory device-controller interface, necessitating a method to verify the memory interface effectively before products leave the factory.
Innovation Solution
A method involving a processing unit that drives signal voltages on IO pins to predefined levels, obtains test results, and stores them in SRAM, enabling a test host to assess the memory interface for errors, with a non-transitory computer program product and apparatus comprising the memory interface, test interface, and processing unit to facilitate this verification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple die stacking is used to reduce package footprint and improve electrical performance, then storage space efficiency and transmission speed are improved, but manufacturing defects in interconnections increase
Solution Approach 1:
The patent implements preliminary testing of the memory interface before final assembly by using a test host to drive test patterns through the memory device and verify signal integrity. This allows defects in interconnections to be detected early in the manufacturing process, enabling selective rejection of defective units before they leave the factory.
2Speed
If multiple die stacking is used to improve electrical performance, then transmission speed and energy efficiency are improved, but the complexity of verifying interface functionality increases
Solution Approach 1:
The memory device performs self-verification through an integrated testing mechanism. The test host sends test patterns through the memory device, which automatically generates and returns test results indicating the status of each IO pin. This self-service approach eliminates the need for complex external verification equipment or manual testing procedures.
Solution Approach 2:
The patent implements a feedback mechanism where the memory device returns test results to the test host through the same interface used for normal operation. The test host receives feedback information about the status of each IO pin and can determine whether the interface is functioning correctly, enabling automated verification without adding significant complexity to the system.
3Ease of manufacture
If conventional single chip packaging is used, then manufacturing simplicity is maintained, but storage space efficiency decreases
Solution Approach 1:
The patent segments the memory interface into multiple independent IO pins, each of which can be tested separately. This segmentation allows the verification process to identify specific defective pins within the stacked die structure, enabling targeted corrective actions or selective rejection without requiring complete replacement of the entire memory device.
Data Source
AI summary
The invention introduces a method for verifying memory interface, performed by a processing unit, to include: driving a physical layer of a memory interface to pull-high or pull-low a signal voltage on each Input-Output (IO) pin thereof to a preset level according to a setting; obtaining a verification result corresponding to each IO pin from the memory interface; and storing each verification result in a static random access memory (SRAM), thereby enabling a testing host to obtain each verification result of the SRAM through a test interface. The testing host may examine each verification result to know whether any unexpected error has occurred in signals on the IO pins of the memory interface.