Nonvolatile Memory Interface Circuit Mode Switching
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Solution Overview
Problem
Current nonvolatile memory devices face inefficiencies in data exchange due to limitations in their input/output interfaces, where commands and addresses can fail to be transferred effectively, leading to decreased interface efficiency.
Innovation Solution
A nonvolatile memory device with a memory interface circuit that receives and processes signals from a memory controller using specific pin configurations and timing protocols, allowing for efficient transfer of commands, addresses, and data by toggling write enable signals to determine signal enable periods and cycle periods, thereby optimizing data exchange.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a conventional input/output interface is used for data exchange between nonvolatile memory device and memory controller, then the interface structure is simple, but data transfer efficiency decreases due to command and address transfer failures
Solution Approach 1:
The memory interface circuit dynamically switches between first and second modes of operation. In the first mode, it receives commands and addresses through data input pins during data transfer. In the second mode, it receives commands and addresses through dedicated command and address input pins. This dynamic mode switching allows the interface to adapt to different transfer requirements, improving data transfer efficiency while maintaining manageable complexity through a unified circuit design that handles both modes.
2Reliability
If commands and addresses are transferred through the same pins used for data exchange, then the interface uses fewer pins, but transfer reliability decreases due to potential conflicts and failures
Solution Approach 1:
The interface circuit segments the signal reception paths into two distinct modes: first mode uses data input pins for command and address reception during data transfer, while second mode uses separate command and address input pins for dedicated command/address transfer. This segmentation allows reliable separation of functions when needed, improving transfer reliability by avoiding signal conflicts, while the ability to switch between modes provides flexibility without requiring permanent separate pin configurations for all operations.
3Adaptability or versatility
If the memory interface circuit operates in a single fixed mode, then the circuit design is simple, but adaptability to different data transfer scenarios is limited
Solution Approach 1:
The memory interface circuit is designed with multi-functionality, capable of operating in both first mode (receiving commands and addresses through data input pins during data transfer) and second mode (receiving commands and addresses through dedicated command and address input pins). This universal design allows a single interface circuit to handle multiple data transfer scenarios and protocol requirements, significantly improving adaptability while avoiding the need for separate dedicated circuits for each mode, thus managing complexity effectively.
Data Source
AI summary
A nonvolatile memory device includes a first pin that receives a first signal, a second pin that receives a second signal, third pins that receive third signals, a fourth pin that receives a write enable signal, a memory cell array, and a memory interface circuit that obtains a command, an address, and data from the third signals in a first mode and obtains the command and the address from the first signal and the second signal and the data from the third signals in a second mode. In the first mode, the memory interface circuit obtains the command from the third signals and obtains the address from the third signals. In the second mode, the memory interface circuit obtains the command from the first signal and the second signal and obtains the address from the first signal and the second signal.