Memory Interface for Multi-Threaded Reconfigurable Fabric
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Solution Overview
Problem
Existing computing systems face limitations in performance and energy efficiency for compute-intensive tasks such as Fast Fourier Transforms and finite impulse response filters, particularly in applications like artificial intelligence and 5G technologies, where dynamic reconfiguration and self-scheduling capabilities are lacking.
Innovation Solution
A multi-threaded, coarse-grained configurable computing architecture with dynamic self-configuration and self-reconfiguration capabilities, incorporating a configuration memory system that includes instruction and instruction index memories for selecting data path configurations, enabling conditional branching, backpressure control, and efficient thread execution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If existing computing systems are used for compute-intensive tasks, then basic computation capability is provided, but performance and energy efficiency are insufficient
Solution Approach 1:
The patent implements dynamic reconfiguration of the computing fabric, allowing the system to adapt its architecture at runtime based on computational requirements. The configurable logic units and interconnection network can be dynamically restructured to optimize performance for different compute-intensive tasks while managing energy consumption efficiently.
Solution Approach 2:
The system changes operational parameters including configuration states of logic units, interconnection network topology, and resource allocation parameters to optimize both performance and energy efficiency. The configuration memory and control logic enable parameter adjustment without physical hardware changes.
2Adaptability or versatility
If dynamic reconfiguration capability is added to computing systems, then adaptability for different applications is improved, but system complexity increases
Solution Approach 1:
The computing fabric is segmented into multiple configurable logic units, each capable of independent configuration. This segmentation allows complex adaptive functionality to be achieved through composition of simpler, independently controllable units, managing overall system complexity while maintaining high adaptability.
Solution Approach 2:
The patent designs universal configurable logic units that can perform multiple functions through software-controlled reconfiguration. A single hardware unit can be programmed to execute different computational tasks, reducing the need for multiple specialized components and thereby managing complexity while enhancing versatility.
3Productivity
If self-scheduling and multi-threading capabilities are implemented, then resource utilization is optimized, but control logic complexity increases
Solution Approach 1:
The computing fabric implements self-scheduling capabilities where the system automatically manages thread allocation and resource assignment without external intervention. The control logic monitors system state and dynamically schedules computational tasks across available resources, optimizing utilization while the modular architecture keeps control logic manageable through localization of scheduling functions.
Data Source
AI summary
Representative apparatus, method, and system embodiments are disclosed for configurable computing. A representative memory interface circuit comprises: a plurality of registers storing a plurality of tables, a state machine circuit, and a plurality of queues. The plurality of tables include a memory request table, a memory request identifier table, a memory response table, a memory data message table, and a memory response buffer. The state machine circuit is adapted to receive a load request, and in response, to obtain a first memory request identifier from the load request, to store the first memory request identifier in the memory request identifier table, to generate one or more memory load request data packets having the memory request identifier for transmission to the memory circuit, and to store load request information in the memory request table. The plurality of queues store one or more data packets for transmission.