Memory Interface Module Multiplexer Demultiplexer IO Width Conversion
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Solution Overview
Problem
Conventional NAND memory systems face challenges in maintaining high IO speed while keeping costs low, as increasing IO channels lead to higher system costs and larger board areas, and faster IO speeds are difficult to meet with existing x8 IO per channel configurations.
Innovation Solution
Implementing an interface module with multiplexer and demultiplexer circuitry to convert between external x16 IO and internal x8 IO, allowing the NAND die to operate at half the IO speed with double the width between the interface chip and the NAND die, maintaining low-cost manufacturing without compromising full system IO speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If x8 IO per channel configuration is used, then system cost is reduced, but IO speed cannot be maintained at high levels
Solution Approach 1:
The interface is segmented into two distinct paths: an external interface path supporting x16 IO width at full system speed, and an internal interface path supporting x8 IO width at half speed. This segmentation allows the system to achieve high IO throughput through the external path while maintaining cost-effectiveness through the internal path configuration.
Solution Approach 2:
The patent transitions from a single-dimensional IO configuration (either x8 or x16) to a two-dimensional configuration where different IO widths and speeds are supported simultaneously in different paths. This dimensional change enables the system to optimize both cost and performance without compromise.
2Speed
If IO channels are increased to maintain high IO speed, then system cost increases and board area increases
Solution Approach 1:
The IO path is segmented to separate high-speed external communication from lower-speed internal communication. By segmenting the interface, the system can use fewer channels for internal operations while maintaining high-speed capability through the external path, thereby reducing overall system complexity and cost.
Solution Approach 2:
An intermediary interface layer is introduced between the external high-speed interface and the internal memory interface. This intermediary layer enables speed negotiation and allows the system to achieve high IO throughput without requiring all internal components to operate at full speed, thus reducing system cost and complexity.
3Productivity
If x16 IO width is used between interface chip and NAND die, then IO throughput is improved, but manufacturing cost increases
Solution Approach 1:
The interface is segmented to provide x16 IO width only where necessary (external interface path) and x8 IO width where sufficient (internal path). This segmentation enables high IO throughput through the external path while avoiding the unnecessary cost of implementing x16 throughout the entire interface chain.
Solution Approach 2:
Different IO widths are applied locally to different parts of the interface: x16 width is used in the external interface path where high throughput is critical, while x8 width is used in the internal path where cost consideration is more important. This local optimization achieves high productivity without uniformly increasing manufacturing cost.
Data Source
AI summary
An embodiment of an apparatus may include a memory package with one or more memory die on an internal input/output (IO) path of the memory package, and an interface module communicatively coupled to the one or more memory die through the internal IO path, the interface module including circuitry to perform IO external to the memory package at a first IO width and a first IO speed, and perform IO internal to the memory package at a second IO width and a second IO speed, wherein one or more of the second IO width is different from the first IO width and the second IO speed is different from the first IO speed. Other embodiments are disclosed and claimed.