Memory Interface Circuit for Noise Detection Without Parity Bits
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing interface circuits face challenges in detecting noise-induced errors during data transmission between circuits, such as memory and memory control circuits, which can lead to increased data volume due to the addition of parity bits for error detection.
Innovation Solution
An interface circuit comprising a first output circuit, a second output circuit, and a comparison circuit that compares the logic level changes of an access signal before and after output, allowing for noise detection without adding parity bits, thereby reducing data volume and maintaining access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a parity bit is added to data to be transmitted/received between memory and memory control circuit, then error detection capability is improved, but data transmission volume increases
Solution Approach 1:
The patent creates a copy of the access signal through two separate output circuits (first and second output circuits) that generate identical signals from the same input. This copied signal path enables error detection by comparing the copied signal with the original, providing reliability improvement without adding data bits to the actual data transmission stream.
Solution Approach 2:
The patent introduces a comparison circuit as an intermediary that receives both the original access signal and the copied access signal, and compares their logic level changes. This intermediary component enables error detection by identifying discrepancies between the original and copied signals, without requiring parity bits to be added to the data itself.
2Reliability
If a parity bit is added to data to be transmitted/received, then error detection capability is improved, but access speed decreases
Solution Approach 1:
The patent creates a parallel copy of the access signal through separate output circuits, enabling simultaneous error detection without sequentially processing parity bits. This parallel copying approach maintains access speed by performing error detection concurrently with data transmission rather than adding sequential overhead.
Solution Approach 2:
The comparison circuit acts as an intermediary that continuously monitors logic level changes in real-time during access operations. This real-time comparison enables error detection without interrupting or slowing down the main access speed, as the comparison occurs in parallel with the normal data flow.
3Reliability
If logic level changes of access signal are monitored to detect noise, then error detection capability is improved, but circuit complexity increases
Solution Approach 1:
The patent uses simple copying of the access signal through identical output circuits to create a reference signal for comparison. This copying approach provides noise detection capability without requiring complex error correction codes or sophisticated monitoring mechanisms, thereby limiting the increase in circuit complexity to just the additional output and comparison components.
Solution Approach 2:
The comparison circuit serves as a simple intermediary that only needs to count and compare logic level changes between two signals. This intermediary function provides effective noise detection through a relatively simple counting and comparison mechanism, avoiding the need for complex error detection algorithms or additional hardware complexity.
Data Source
AI summary
An interface circuit comprising: a first output circuit configured to allow an access signal to be input thereto and output the access signal to a storage circuit, the access signal capable of being changed to one logic level or the other logic level for accessing the storage circuit; a second output circuit configured to output the access signal outputted from the first output circuit; and a comparison circuit configured to compare the number of times a logic level of the access signal inputted to the first output circuit is changed and the number of times a logic level of the access signal outputted from the second output circuit is changed, and output a comparison signal indicating whether predetermined access has been performed based on the access signal inputted to the first output circuit, after at least a part of the access signal is inputted to the first output circuit.