Memory Interface Input Circuits for Parallel Offset Correction

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Solution Overview

Problem

Existing memory systems face challenges in efficiently correcting voltage and delay offsets during training operations, leading to increased resource consumption and latency, particularly in chip interface training.

Innovation Solution

A memory system with a buffer chip and input circuits that can independently correct voltage and delay offsets in non-volatile memory devices during training operations, using loops to adjust input buffers and repeaters, allowing parallel correction without feedback from the memory controller.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Measurement precision

If traditional memory systems use memory controller feedback for offset correction during training operations, then correction accuracy can be maintained, but training operation time increases and resource consumption increases

Engineering Contradiction:

Improveoffset correction accuracyVSAvoidtraining operation time

Core Design Contradiction:

Measurement precisionVSLoss of time

Solution Approach 1:

The input circuit performs self-training on voltage offset and delay offset corrections using its own internal resources (DQS signal, input buffers, repeater, and offset correction circuits) without requiring feedback from the memory controller. This self-service mechanism allows the circuit to autonomously calibrate itself during training operations, reducing the time burden on the memory controller and accelerating the overall training process while maintaining correction accuracy.

Inventive Principle:

Principle #25Self-service

2Device complexity

If memory controller performs centralized offset correction, then system control is simplified, but processing capability and power consumption increase

Engineering Contradiction:

Improvecontrol structure simplicityVSAvoidpower consumption

Core Design Contradiction:

Device complexityVSUse of energy by moving object

Solution Approach 1:

The offset correction function is segmented from the memory controller and distributed to individual input circuits. Each input circuit contains its own voltage offset correction circuit and delay offset correction circuit, allowing parallel independent correction operations. This segmentation reduces the processing burden and power consumption of the memory controller while maintaining simplified overall control architecture.

Inventive Principle:

Principle #1Segmentation

3Quantity of substance

If offset correction is performed sequentially, then resource requirements are reduced, but training operation time increases

Engineering Contradiction:

Improveresource requirementsVSAvoidtraining operation speed

Core Design Contradiction:

Quantity of substanceVSProductivity

Solution Approach 1:

The input circuit performs voltage offset correction and delay offset correction as preliminary actions during the training operation phase, before normal memory operations begin. By completing both correction types in advance using the DQS signal available during training, the system eliminates the need for separate correction phases, thereby accelerating training operation speed without requiring additional resources beyond what is already allocated for training.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS20250307136A1Input circuit, memory interface circuit and memory system

Publication Date: 2025.10.02 SAMSUNG ELECTRONICS CO LTD

AI summary

An input circuit includes a first input buffer connected to a corresponding data pin, a second input buffer connected to a data strobe pin, and a repeater configured to delay an output signal of the first input buffer, and further includes a first loop configured to correct a voltage offset of each of the first input buffer and the second input buffer, and a second loop configured to correct a delay offset of the repeater.