Semiconductor Memory Interface Registers with Paged Address Spaces
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Solution Overview
Problem
Existing semiconductor memory devices face challenges in allocating sufficient feature register space for interface chips due to increasing demands for high-speed operations and the need for numerous functional settings, leading to insufficient space for parameter data storage.
Innovation Solution
The implementation of a feature register group in the interface chip with multiple pages that can be designated using a specific address value, allowing for expanded storage capacity by interpreting command sequences for page designation, thereby increasing the subspace available for parameter data without reducing memory chip allocations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a feature register group is provided in the interface chip for functional settings, then the storage capacity for parameter data is increased, but the address space becomes insufficient due to overlapping with memory chip address spaces
Solution Approach 1:
The feature register group in the interface chip is divided into multiple pages (first page, second page, etc.), each with its own address space. This segmentation allows the interface chip to have sufficient storage capacity for parameter data while avoiding address space conflicts with memory chips, as each page can be independently addressed and managed.
Solution Approach 2:
The patent introduces a page dimension to the address space structure. Instead of using a flat address space that conflicts with memory chip addresses, the feature register group uses a hierarchical structure with pages, effectively adding another dimension to the addressing scheme. This allows the interface chip to access its parameter data storage without interfering with memory chip address spaces.
2Adaptability or versatility
If the feature register group uses common address spaces with memory chips, then compatibility is maintained, but the interface chip loses sufficient space for its own parameter data
Solution Approach 1:
The feature register group is segmented into multiple pages, creating dedicated address spaces for the interface chip that are separate from memory chip address spaces. This segmentation maintains compatibility through standardized command sequences while ensuring the interface chip has sufficient independent space for its parameter data storage needs.
Solution Approach 2:
The patent introduces a page number as an intermediary element between the command sequence and the actual register address. The command sequence includes a page number that mediates the address translation, allowing the interface chip to access its feature registers without direct conflicts with memory chip address spaces, thus maintaining compatibility while providing sufficient space.
3Quantity of substance
If multiple pages are introduced in the feature register group, then storage capacity is expanded, but the command sequence complexity increases
Solution Approach 1:
The command sequence is designed to be universal and multi-functional, handling both page designation and parameter data storage in a single standardized format. The same command sequence structure is used whether designating a page or storing parameter data, reducing the need for multiple specialized command formats and minimizing the increase in complexity while enabling expanded storage capacity through multiple pages.
Data Source
AI summary
According to one embodiment, a semiconductor memory device includes a terminal group, a first device, and a second device. The first device includes a first register group to which a first address space is mapped and a memory cell array. The second device is provided between the terminal group and the first device. The second device includes a second register group. The second register group includes multiple pages to which common second address spaces exclusive of the first address space are mapped. When the second device receives a command sequence of a setting command, the second device identifies, based on the command sequence of the setting command, a storage destination page of parameter data from among the multiple pages when an address included in the command sequence of the setting command is a first value.