Memory Access Interface Clocking for Multi-Mode Phase Calibration
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Solution Overview
Problem
Conventional memory access technologies, such as single data rate (SDR) and non-volatile double data rate (NVDDR), face challenges in supporting varying speeds and signal calibration, which limits their ability to meet increasing bandwidth requirements.
Innovation Solution
A memory access interface device with a clock generation circuit and multiple access signal transmission circuits, including first and second clock frequency division circuits, phase adjusting circuits, and duty cycle adjusting circuits, to generate independent reference clock signals with adjustable phases and duty cycles, enabling precise signal calibration and access to memory devices across different speed modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional SDR configuration is used, then device complexity is low, but speed and bandwidth are limited
Solution Approach 1:
The interface device is segmented into multiple independent access signal transmission circuits, each capable of operating at different speeds. This allows the system to achieve high-speed NVDDR operation when needed while maintaining compatibility with lower-speed SDR modes, resolving the contradiction between speed and complexity by providing speed-specific pathways without requiring the entire system to operate at maximum complexity continuously.
Solution Approach 2:
The interface device dynamically switches between different operating modes (SDR, NVDDR1, NVDDR2, etc.) based on the memory device being accessed. The clock generation circuit and signal transmission circuits are designed to adapt their operation dynamically, enabling the system to achieve high speed when required while maintaining low complexity for standard operations, thus resolving the speed-complexity trade-off.
2Adaptability or versatility
If NVDDR configuration with higher speed is used, then bandwidth requirement is met, but support for all speed modes and signal calibration becomes difficult
Solution Approach 1:
Each access signal transmission circuit is designed with universal functionality to handle multiple speed modes (SDR, NVDDR1, NVDDR2, etc.) through a unified architecture. The circuits include integrated phase adjusting and duty cycle adjusting capabilities that work across all modes, eliminating the need for separate calibration mechanisms for each speed mode and thereby reducing overall complexity while maintaining broad adaptability.
Solution Approach 2:
The interface device uses parameter-adjustable components including phase adjusting circuits and duty cycle adjusting circuits that can be configured for different operating modes. These parameters (phase, duty cycle) are automatically calibrated based on the selected mode, enabling the system to support all speed modes without manual intervention and reducing the complexity of multi-mode support.
3Measurement precision
If multiple independent reference clock signals with adjustable phase are generated, then phase adjustment precision is improved, but clock generation circuit complexity increases
Solution Approach 1:
The clock generation function is segmented into multiple independent reference clock signal generators, each dedicated to a specific access signal transmission circuit. This segmentation allows each clock generator to be optimized for its specific function with precise phase control, while the overall system manages complexity through functional separation rather than requiring one overly complex universal clock generator.
Solution Approach 2:
Phase adjusting circuits serve as intermediary components between the reference clock signals and the access signals. These intermediaries provide precise phase control by adjusting the phase of access signals relative to their corresponding clock signals, achieving high measurement precision without requiring the clock generation circuit itself to be overly complex. The intermediaries handle the fine-tuning functionality that would otherwise complicate the clock generation.
Data Source
AI summary
A memory access interface device that includes a clock generation circuit that generates reference clock signals according to a source clock signal and access signal transmission circuits are provided. Each of the access signal transmission circuits includes a first and a second clock frequency division circuits, a phase adjusting circuit and a duty cycle adjusting circuit. The first and the second clock frequency division circuits sequentially divide the frequency of one of the reference clock signals to generate a first and a second frequency divided clock signals respectively. The phase adjusting circuit adjusts the phase of an access signal according to the second frequency divided clock signal to generate a phase-adjusted access signal. The duty cycle adjusting circuit adjusts the duty cycle of the phase-adjusted access signal to be a half of the time period to generate an output access signal to access a memory device.