Memory Access Interface Phase Training for Device Variation
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Solution Overview
Problem
Memory devices, such as LVDDR memory devices, exhibit varying parameters due to different processing, packaging, and board conditions, leading to low yield when timing parameters are uniformly set, necessitating a training process to maintain accessing accuracy.
Innovation Solution
A memory access interface device with a clock generation circuit, transmitter, and signal training circuit that adjusts timing reference signals through a training process, comparing training signals with data signals to determine valid phases, thereby optimizing access signal timings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If timing parameters are set to be the same among all memory devices, then device complexity is reduced, but manufacturing precision and yield deteriorate due to parameter variations
Solution Approach 1:
The patent applies parameter changes by dynamically adjusting timing parameters (phase and delay values) of access signals based on actual memory device characteristics. The training process modifies these parameters loop-by-loop to converge on optimal values that compensate for manufacturing variations, thereby maintaining high access accuracy without requiring complex manual configuration.
Solution Approach 2:
The memory system performs self-training by automatically detecting and adapting to individual device characteristics through an embedded training process. The system self-adjusts timing parameters without external intervention, using feedback mechanisms to converge on optimal settings for each specific memory device, thus achieving high precision while keeping the system relatively simple.
2Manufacturing precision
If a training process is implemented to optimize timing parameters, then manufacturing precision and yield are improved, but training complexity and processing time increase
Solution Approach 1:
The training process is segmented into multiple loops, each focusing on adjusting specific timing parameters (phase and delay) independently. This segmentation allows the complex training to be broken down into manageable iterations, where each loop refines particular parameters based on feedback, reducing the overall complexity by organizing the training process into structured phases.
Solution Approach 2:
The patent implements feedback mechanisms where the system monitors access signal quality during training and uses this information to adjust timing parameters in subsequent loops. This feedback-driven approach simplifies the training process by automatically guiding parameter adjustments toward optimal values, reducing the need for complex manual control while maintaining high precision.
3Manufacturing precision
If timing parameters are individually optimized for each memory device, then manufacturing precision is improved, but productivity and training time increase
Solution Approach 1:
The system performs preliminary training in a dedicated training mode before normal operation begins. During this preliminary phase, timing parameters are pre-optimized for each memory device through automated detection and adjustment. By completing this training beforehand, the system prepares optimal parameters in advance, enabling faster and more efficient operation during actual use without requiring continuous training intervention.
Solution Approach 2:
The training process operates periodically in discrete loops, where each loop iterates through a set of timing parameter adjustments and evaluations. This periodic structure allows the system to efficiently converge on optimal parameters through repeated cycles of adjustment and verification, improving training speed by utilizing the periodic nature of the iterations to systematically explore the parameter space.
Data Source
AI summary
The present disclosure discloses a memory access interface device. A clock generation circuit generates reference signals. A transmitter transmits an output command and address signal to a memory device according to the reference signals. A signal training circuit executes a training process in a training mode that includes steps outlined below. A training signal is generated such that the training signal is transmitted as the output command and address signal. The training signal and the data signal generated by the memory device are compared to generate a comparison result indicating whether the data signal matches the training signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of at least one of the reference signals to be one of a plurality of under-test phases to execute a new loop of the training process until all the under-test phases are trained.