Memory Interface Pre-Emphasis Calibration for Low-Distortion Links
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Solution Overview
Problem
Existing memory interface circuits face challenges in minimizing data distortion during transmission between memory devices and host devices, particularly in volatile memory devices like DRAM and SRAM, which lose data when power is off.
Innovation Solution
The implementation of a memory interface circuit with a calibration loop circuit and a transmitter that generates a delay code to control variable capacitors, performing pre-emphasis operations on transmission signals to minimize distortion by adjusting capacitance values based on the delay code.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pre-emphasis operations are performed to minimize signal distortion during transmission, then transmission reliability is improved, but chip area increases due to additional calibration circuits and variable capacitors
Solution Approach 1:
The patent applies local quality by implementing pre-emphasis calibration specifically in the memory interface circuit where signal distortion occurs, rather than throughout the entire system. The calibration loop circuit and variable capacitors are localized to the transmission path between memory device and host device, minimizing the area impact while achieving reliable transmission only where needed.
Solution Approach 2:
The patent implements preliminary action through the calibration loop circuit that performs pre-emphasis calibration before actual data transmission. The delay code is generated in advance based on phase differences between clock signals, and variable capacitors are pre-adjusted to optimal values, ensuring transmission reliability is established before data transfer begins.
2Reliability
If calibration loop circuits and variable capacitors are added to perform pre-emphasis operations, then signal distortion is reduced, but device complexity increases
Solution Approach 1:
The calibration loop circuit serves multiple functions: it generates the delay code, controls the variable capacitors, and compensates for signal distortion. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in device complexity while achieving improved signal transmission quality.
Solution Approach 2:
The patent changes the capacitance parameter of variable capacitors dynamically based on the generated delay code. By adjusting the capacitance values, the circuit compensates for signal distortion without requiring complex structural modifications, thus improving transmission quality while controlling circuit complexity through parameter adjustment rather than structural complexity.
3Measurement precision
If variable capacitors are used for pre-emphasis operations, then transmission accuracy is improved, but manufacturing precision requirements increase
Solution Approach 1:
The calibration loop circuit implements feedback by monitoring the phase difference between clock signals and adjusting the delay code accordingly. This feedback mechanism compensates for variations in capacitor characteristics, allowing the system to achieve high transmission accuracy even when manufacturing precision of individual capacitors varies, as the feedback loop corrects for these deviations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables accurate and low-power pre-emphasis operations, reducing signal distortion and ensuring reliable data transmission with minimal chip area requirements.
Implementation Method 1
generating a delay signal by inverting and delaying the first pulse signal using a first variable capacitor
Implementation Method 2
perform a pre-emphasis operation on the transmission signal based on a capacitance of a second variable capacitor, which changes in response to changes in the delay code
Data Source
AI summary
A memory interface circuit includes a calibration loop circuit configured to generate: a first pulse signal in response to a first clock signal, a second pulse signal in response to the first clock signal and a second clock signal, a delay signal by inverting and delaying the first pulse signal using a first variable capacitor, and a delay code based on the first and second pulse signals and the delay signal. A first transmitter is provided, and configured to generate a transmission signal in response to a data signal received from a volatile memory device, and perform a pre-emphasis operation on the transmission signal based on a capacitance of a second variable capacitor, which changes in response to changes in the delay code.