Memory Interface Routing Circuits for Read-Write Turnaround Delay
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Solution Overview
Problem
Memory systems experience turnaround delays when transitioning from read to write operations due to round-trip times and interface delays in bidirectional links, leading to reduced data rates and efficiency.
Innovation Solution
The implementation of a memory system with configurable routing circuits and queues that allow for simultaneous read and write operations without mode changes, using multiplexers and interface circuits to manage data flow on bidirectional links, eliminating turnaround delays by ensuring continuous data communication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If half-duplex communication is used on bidirectional links, then the link can be shared for both read and write operations, but turnaround delays occur when transitioning between read and write modes, reducing effective data rate
Solution Approach 1:
The memory controller is divided into multiple interface circuits (first interface circuit and second interface circuit) that can operate independently. Each interface circuit has its own queue for data buffering, allowing simultaneous read and write operations without requiring mode switching, thereby eliminating turnaround delays while maintaining link sharing capability
Solution Approach 2:
Queues are introduced as intermediary buffering structures between the interface circuits and the memory core. These queues decouple the read and write operations, allowing data to be transferred asynchronously without requiring the bidirectional link to switch directions, thus eliminating turnaround delays while preserving the ability to share links
2Reliability
If gaps are included in the data stream to account for turnaround delay, then read-write transitions can be managed, but the effective data rate and communication efficiency are reduced
Solution Approach 1:
Multiple interface circuits operate simultaneously and independently, with each maintaining continuous data transfer operations. The first interface circuit performs read operations while the second interface circuit performs write operations at the same time, ensuring continuous useful action without gaps in the data stream, thereby maintaining high effective data rate while reliably managing read-write transitions
3Adaptability or versatility
If mode changes are required for read-write operations, then bidirectional link utilization is achieved, but communication efficiency and data rate are reduced due to turnaround delays
Solution Approach 1:
The communication interface is segmented into multiple independent interface circuits, each handling specific operations (read or write) continuously. This segmentation allows the system to utilize the bidirectional link for both read and write operations simultaneously without requiring mode changes, thereby maintaining high adaptability while achieving excellent communication efficiency
Solution Approach 2:
The system changes the operational parameter from sequential mode switching to parallel simultaneous operation. By configuring multiple interface circuits to operate at the same time with different data directions, the system achieves full bidirectional link utilization while eliminating turnaround delays, thus maximizing both adaptability and productivity
Data Source
AI summary
Embodiments of a memory system that communicates bidirectional data between a memory controller and a memory IC via bidirectional links using half-duplex communication are described. Each of the bidirectional links conveys write data or read data, but not both. States of routing circuits in the memory controller and the memory IC are selected for a current command being processed so that data can be selectively routed from a queue in the memory controller to a corresponding bank set in the memory IC via one of the bidirectional links, or to another queue in the memory controller from a corresponding bank set in the memory IC via another of the bidirectional links. This communication technique reduces or eliminates the turnaround delay that occurs when the memory controller transitions from receiving the read data to providing the write data, thereby eliminating gaps in the data streams on the bidirectional links.