Memory Interface Circuit Power Management via Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The increasing demand for larger capacity memory systems is hindered by power dissipation limitations in memory circuits and the inability of power supply systems to deliver sufficient power, particularly in systems with reduced memory module slots.
Innovation Solution
A memory circuit power management system that uses an interface circuit to simulate virtual memory circuits with different power behaviors, allowing for reduced average and peak power consumption by interfacing physical memory circuits with a system, enabling power management operations such as power saving commands and latency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If larger capacity memory circuits are used to meet increasing memory capacity requirements, then memory capacity is improved, but power dissipation per unit volume increases and exceeds power supply capabilities
Solution Approach 1:
The physical memory circuits are divided into multiple smaller memory circuits that can be independently controlled. The interface circuit manages these segmented memory circuits separately, allowing selective activation and power management of individual circuits based on system needs, thereby reducing overall power dissipation while maintaining large aggregate capacity.
Solution Approach 2:
The interface circuit dynamically manages the operational states of multiple physical memory circuits, transitioning them between active and power-saving modes based on access patterns and system requirements. This dynamic power management allows the system to optimize between capacity utilization and power dissipation in real-time.
2Quantity of substance
If more memory circuits are activated to provide larger capacity, then memory capacity is improved, but peak power consumption increases beyond power supply delivery capability
Solution Approach 1:
Memory capacity is provided through multiple segmented physical memory circuits that can be activated individually or in groups. The interface circuit controls which segments are active at any given time, ensuring that peak power consumption remains within supply capabilities while still providing the required total capacity when needed.
Solution Approach 2:
The interface circuit implements periodic activation and deactivation of memory circuits based on access patterns, allowing memory circuits to enter power-saving states between accesses. This periodic operation reduces peak power consumption while maintaining the ability to provide full capacity when required.
3Loss of energy
If power management operations are implemented to reduce power consumption, then power dissipation is improved, but system complexity increases due to additional control mechanisms
Solution Approach 1:
The interface circuit serves multiple functions simultaneously: it interfaces between the system and physical memory circuits, manages power distribution, controls activation/deactivation sequences, and provides virtualization. By consolidating these functions in a single interface component, the patent reduces overall system complexity while achieving effective power management.
Solution Approach 2:
The interface circuit acts as an intermediary layer between the system and physical memory circuits, absorbing the complexity of power management control mechanisms. This intermediary handles all power-related control operations, shielding the rest of the system from complexity while enabling sophisticated power dissipation management.
Data Source
AI summary
A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual memory circuit with a first power behavior that is different from a second power behavior of the physical memory circuits.


