Memory Interface Circuitry with Shared Data Strobe Signal Phase Shifting
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Solution Overview
Problem
Programmable integrated circuits face challenges in synchronizing data and clock signals with memory devices due to varying circuit board trace lengths, leading to unpredictable timing characteristics, which necessitates a cost-effective solution for phase shifting data strobe signals.
Innovation Solution
The memory interface circuitry includes first and second latching circuits, delay circuits, and a quarter clock cycle shifting circuit to align data strobe signals with data signals, allowing for flexible operation with multiple memory devices and protocols, reducing the need for multiple 90° phase shift circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a dedicated 90° phase shift circuit is used for each memory device, then data strobe signal synchronization is achieved, but area overhead and cost increase significantly
Solution Approach 1:
The patent merges multiple 90° phase shift circuits into a single shared phase shift circuit that serves multiple memory devices. The data strobe signal from any memory device is routed through this shared circuit, eliminating the need for separate phase shift circuits for each device and significantly reducing area overhead.
Solution Approach 2:
The shared phase shift circuit is designed to handle data strobe signals from multiple memory devices universally. It can process and synchronize signals from different memory devices with varying trace lengths, making a single circuit perform the function that previously required multiple dedicated circuits.
2Manufacturing precision
If circuit board trace lengths are standardized, then timing characteristics become predictable, but adaptability to different system configurations is reduced
Solution Approach 1:
The patent introduces delay adjustment mechanisms that allow the phase shift circuit to dynamically adapt its timing characteristics. By adjusting the delay amount based on the specific trace lengths and timing requirements of different memory devices, the system maintains predictability while adapting to various configurations without requiring standardized trace lengths.
Solution Approach 2:
The system changes the delay parameter of the phase shift circuit based on the specific timing requirements of different memory devices. This allows the circuit to compensate for varying trace lengths and maintain synchronized data strobe signals across different system configurations, balancing predictability with adaptability.
3Reliability
If multiple 90° phase shift circuits are used, then each memory device receives proper signal timing, but cost increases
Solution Approach 1:
The patent combines multiple phase shift circuits into a single shared resource, directly reducing the component count and manufacturing cost. The shared circuit maintains signal timing accuracy for all memory devices while eliminating the redundant cost of multiple separate circuits.
Solution Approach 2:
Instead of implementing separate physical phase shift circuits for each memory device, the system uses a single shared circuit that is logically replicated or time-multiplexed to serve multiple devices, reducing hardware cost while maintaining the functional capability of proper signal timing for each device.
Data Source
AI summary
An integrated circuit may include memory interface circuitry for communicating with off-chip memory. The memory interface circuitry may receive data signals and data strobe signals from different memory devices via respective data ports and data strobe ports. The memory interface circuitry may be operable in at least first and second modes. In the first mode, data signals from each memory device may be received at two respective data ports while the data strobe signal from one memory device is used to clock the data signals at two corresponding read capture registers. In the second mode, data signals from first and second memory devices may be received via first and second data ports, respectively. The data strobe signal from the first memory device may be ignored while the data strobe signal from the second memory device is used to clock the data signals at two corresponding read capture registers.