Memory Interface Signal Locking for Stable Chip Enable Control

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Solution Overview

Problem

Previous IOE devices in memory sub-systems face issues with decreased load capability and unexpected behavior due to configuration signals altering memory resource functionality, leading to performance degradation and data retrieval errors.

Innovation Solution

Implementing a signal locking component in the IOE device to prevent certain signals, such as chip enable signals, from propagating to the back end, thereby filtering out configuration signals that could disrupt memory resources.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of operation

If configuration signals are allowed to propagate to memory devices through the IOE device, then the IOE device can be configured by the host system, but the memory devices experience unexpected behavior and performance degradation

Engineering Contradiction:
ImproveIOE device configuration capabilityVSAvoidmemory device operation stability
Core Design Contradiction:
Ease of operationVSReliability

Solution Approach 1:

The patent segments the signal propagation path by introducing a signal locking component that divides the chip enable signal into two independent paths: one for configuration signals (unlocked state) and one for data signals (locked state). This segmentation allows configuration signals to reach the IOE device while preventing data signals from reaching memory devices, resolving the contradiction between configuration capability and operational stability.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The signal locking component acts as an intermediary between the host system and memory devices. It selectively filters and locks data signals while allowing configuration signals to pass through, mediating the interaction to prevent harmful signal propagation to memory devices while preserving necessary configuration functionality.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If the signal locking component locks the chip enable signal, then data signals are prevented from reaching memory devices, but configuration signals cannot be transmitted

Engineering Contradiction:
Improveprotection of memory devices from unintended signal alterationsVSAvoidsignal transmission flexibility
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The signal locking component dynamically adjusts its locking state based on the signal type. It maintains a locked state for data signals to protect memory devices while transitioning to an unlocked state for configuration signals to enable proper transmission. This dynamic behavior resolves the contradiction between protection and adaptability.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent applies local quality by treating different signal types differently at the signal locking component. Configuration signals receive one handling (unlocked) while data signals receive another handling (locked), allowing the system to simultaneously achieve protection and signal transmission flexibility through localized differentiated processing.

Inventive Principle:
Principle #3Local quality

3Adaptability or versatility

If configuration signals alter memory resource functionality, then the IOE device can adapt to different memory configurations, but data retrieval errors occur and performance degrades

Engineering Contradiction:
Improvememory configuration adaptabilityVSAvoiddata retrieval performance
Core Design Contradiction:
Adaptability or versatilityVSProductivity

Solution Approach 1:

The signal locking component extracts and separates configuration signals from data signals, allowing configuration signals to be processed independently without affecting data transmission paths. This extraction prevents configuration signal interference with data retrieval operations, maintaining both adaptability and productivity.

Inventive Principle:
Principle #2Taking out (Extraction)

Data Source

PatentUS12547348B2Signal locking
Publication Date: 2026.02.10 MICRON TECHNOLOGY INC
  • US12547348B2 patent drawing
  • US12547348B2 patent drawing
  • US12547348B2 patent drawing

AI summary

A method includes receiving, by a memory device interface, a first operation command targeted for receipt by a memory device coupled to the memory device interface causing, responsive to receiving the first operation command, a chip enable signal to be asserted in a first state to filter commands received by the memory device interface that are targeted for subsequent receipt by the memory device, receiving, by the memory device interface, a second operation command targeted for receipt by a memory device coupled to the memory device interface, and causing, responsive to receiving the second operation command, the chip enable signal to be asserted in a second state to allow commands received by the memory device interface that are targeted for subsequent receipt by the memory device to be received by the memory device.