Memory Interface Architecture with Task Processor for Lower Host Latency
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Solution Overview
Problem
Existing memory systems face delays and inefficiencies when the host computing device is locked up or delayed while waiting for data to be acquired in response to read commands, particularly due to the burden of tasks such as data reception, storage, and processing in volatile and non-volatile memory systems.
Innovation Solution
A computing system with a task processor that offloads data reception, storage, and processing tasks from the host CPU by integrating a task processor with DRAM and non-volatile memory on a single printed circuit board, allowing the task processor to handle data sorting, indexing, and storage in DRAM, while the host CPU remains free to perform other tasks.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If the host CPU handles data reception and storage tasks directly, then the system can operate with simpler architecture, but the host CPU becomes locked up or delayed while waiting for data acquisition
Solution Approach 1:
A task processor is introduced as an intermediary component between the host CPU and memory devices. The task processor receives data from network interfaces and stores it in non-volatile memory independently of the host CPU, eliminating the bottleneck where the host CPU waits for data acquisition. This mediator architecture allows the host CPU to continue executing instructions without being blocked by data storage operations.
Solution Approach 2:
The system is segmented into distinct functional components: a task processor that handles data reception and storage, and a host CPU that executes instructions. By separating these functions, the patent eliminates the dependency chain where the host CPU must wait for data to be stored in memory, thereby reducing latency and improving operational continuity.
2Productivity
If the host CPU performs all data processing tasks, then the system architecture remains simple, but system efficiency decreases due to increased processing burden on the host
Solution Approach 1:
The task processor serves as an intermediary that handles data processing tasks such as receiving data from network interfaces and storing it in non-volatile memory. This mediator component offloads redundant processing tasks from the host CPU, improving system productivity while adding only moderate architectural complexity through a dedicated processing unit.
Solution Approach 2:
The task processor is designed to autonomously perform data reception and storage operations without requiring continuous intervention from the host CPU. This self-service capability allows the task processor to independently manage data flow tasks, thereby improving system efficiency by reducing the processing burden on the host CPU.
3Speed
If data is stored directly in non-volatile memory without processing, then data storage is faster, but data accessibility and organization are reduced
Solution Approach 1:
The task processor performs preliminary actions on data before storing it in non-volatile memory, including indexing and sorting operations. By preparing and organizing data in advance during the storage process, the system achieves both fast storage speeds and improved data accessibility, as the data is pre-organized in a manner that facilitates quick retrieval and processing.
Data Source
AI summary
Provided is a system comprising a first interface configured to receive first data from an external computing device, non-volatile memory operatively coupled to the first interface, and a second interface configured to communicate with a host computing device. The system also includes dynamic random-access memory (DRAM) operatively coupled to the second interface, a memory controller operatively coupled to the second interface and the DRAM and configured to control a transfer of information between the DRAM and the host computing device through the second interface, and processing circuitry at least configured to store the first data received through the first interface in the non-volatile memory.