Memory Access Interface Timing Calibration for LPDDR Yield
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The variability in timing parameters of low power double data rate (LPDDR) synchronous dynamic random access memory devices during processing, packaging, and integration affects data access accuracy, leading to low yield and the need for a training process to set optimal timing parameters.
Innovation Solution
A memory access interface device with a clock generation circuit, transmitting circuit, receiving circuit, and signal training circuit that generates training signals and compares them with read signals to determine valid phases, modifying timing reference signals through a series of training loops to achieve accurate data transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If timing parameters are set to be the same among memory devices, then device complexity is reduced, but manufacturing precision deteriorates due to parameter variations during processing and packaging
Solution Approach 1:
The patent applies preliminary action by performing a training process before normal operation to determine optimal timing parameters. The memory access interface device executes a training mode that iteratively adjusts timing parameters (such as write level delay and read delay) before settling on final values, thereby pre-configuring the device to compensate for manufacturing variations without requiring complex per-device tuning during production
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting timing parameters during the training process. The system modifies parameters such as write level delay (WLD), read delay (RD), and clock phase offsets based on comparison results between transmitted and received training data, thereby adapting to specific device characteristics and achieving accurate data access without uniform timing configuration
2Manufacturing precision
If a training process is implemented to obtain preferable timing parameters, then manufacturing precision is improved, but productivity deteriorates due to additional processing time
Solution Approach 1:
The patent applies feedback by using comparison results from training data transmission to guide subsequent parameter adjustments. The system transmits training data, compares the transmitted data with received data to determine accuracy, and uses this feedback to iteratively refine timing parameters until optimal values are achieved, thereby systematically improving data access accuracy while controlling the training process
Solution Approach 2:
The training process is performed as a preliminary action before normal memory operation begins. By completing parameter optimization in advance during initialization, the system ensures high productivity during subsequent data access operations without repeated training cycles, thereby improving overall yield rate while maintaining data access accuracy
3Productivity
If timing parameters are uniformly configured without training, then productivity is improved, but measurement precision deteriorates in determining optimal timing phases
Solution Approach 1:
The memory access interface device performs self-service by automatically determining its own optimal timing parameters through the training process. The device uses its own resources (transmitting circuit, receiving circuit, comparison circuit) to conduct training, measure timing accuracy, and adjust parameters without requiring external intervention, thereby achieving both high productivity and precise timing parameter determination
Data Source
AI summary
The present disclosure discloses a memory access interface device. A signal training circuit is configured for performing following steps. A transmitting circuit transmits a training data signal and a training data strobe signal as an output data signal and an output data strobe signal to a memory device according to timing reference signals. A read data signal from the memory device is received. The training data signal and the read data signal are compared to generate a comparison result indicating whether the read data signal matches the training data signal. The comparison result is stored. The clock generation circuit is controlled to modify a phase of one of the timing reference signals, further modifying the timing of one of the training data signal and the training data strobe signal, to be one of under-test phases to execute a new loop of a training process.