Memory Interface Timing Correction for NAND Flash PVT Variations
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Solution Overview
Problem
NAND-type flash memory systems face challenges in maintaining accurate data operations due to process, voltage, and temperature (PVT) variations, which cause distortions in clock and data signals, leading to setup and hold violations and reduced operational success rates.
Innovation Solution
A system that includes a clock interval oscillator circuit to detect changes in the delay between data strobe and data signals, allowing for realignment and retraining of the memory interface to compensate for PVT-induced variations, thereby ensuring optimal timing and reducing errors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If non-volatile memory systems operate at higher speeds with advanced technologies, then productivity and data operation speed improve, but timing margins decrease making operations more susceptible to PVT variations and errors
Solution Approach 1:
The patent performs write training operations before actual data writing to pre-determine optimal write timing. The controller conducts training writes at different timing positions, evaluates success rates, and selects the optimal timing in advance. This preliminary action establishes a baseline timing that compensates for PVT variations before production operations begin, ensuring high-speed operations maintain reliability.
Solution Approach 2:
The system continuously monitors write operation success rates and uses this feedback to adjust write timing dynamically. When write errors are detected, the controller modifies the write timing based on the observed error patterns and re-attempts the operation. This closed-loop feedback mechanism ensures that timing adjustments are made in real-time to maintain optimal operation despite PVT variations.
2Device complexity
If write timing is fixed to simplify control, then device complexity is reduced, but the system cannot adapt to PVT variations causing increased write errors
Solution Approach 1:
The patent implements dynamic write timing adjustment where the controller modifies write timing based on detected PVT variations and write error patterns. Instead of a fixed timing, the system continuously adapts the write timing position during operation. This dynamic adjustment allows the system to respond to changing conditions without requiring complex hardware modification circuits, maintaining simplicity while improving adaptability.
Solution Approach 2:
The system changes the write timing parameter dynamically based on operating conditions. The controller monitors write success rates and PVT variations, then adjusts the write timing parameter to optimal values. This parameter adaptation allows a single control mechanism to handle varying conditions without increasing device complexity, as only the timing parameter needs modification rather than the overall control architecture.
3Reliability
If the system performs extensive training and error correction operations, then write reliability improves, but loss of time increases due to additional operations required
Solution Approach 1:
The patent performs training writes at a limited number of specific timing positions rather than exhaustively testing all possible timing values. The controller selects key training positions that provide sufficient coverage of the timing range needed to handle PVT variations. This partial action approach achieves adequate adaptation without the time cost of comprehensive training, balancing reliability improvement with time efficiency.
Solution Approach 2:
The system performs write training operations once during initialization or when PVT variations are detected, establishing optimal timing parameters in advance. After the preliminary training is complete, normal write operations proceed using the pre-determined timing without requiring continuous correction attempts. This preliminary action concentrates the time investment in training rather than分散ing it across numerous correction operations during normal operation.
Data Source
AI summary
Systems and methods are provided for correcting errors in unmatched memory devices. Various embodiments herein train a memory interface to determine a duty cycle timing for a clock signal in a data window formed by a data signal in a memory cell. The duty cycle timing identifies an initial trained timing in the data window at which a setup portion and a hold portion of the data window are approximately equal in length when the trigger signal is received at the initial trained timing. The embodiments herein also identify an event that shifts the duty cycle timing away from the initial trained timing, and triggers a retraining of the memory interface based on a determination that at least one of two points defined about the initial trained timing fails a two-point sampling.