Memory Interface Timing Retiming for Skew-Resilient DDR Storage
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Solution Overview
Problem
As the capacity and speed of storage devices increase, their reliability decreases due to increased resistance components and skew, necessitating a method to enhance reliability without compromising operating speed.
Innovation Solution
A storage device with a semiconductor memory device and a memory controller that includes an interface chip capable of detecting locking delays to generate timing signals, thereby reducing skew and improving data transmission reliability during write and read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the capacity and speed of storage devices are increased by overlapping semiconductor memory chips, then the capacity and speed are improved, but the reliability deteriorates due to increased resistance components and skew
Solution Approach 1:
The patent applies preliminary action by detecting the locking delay between timing signals in advance during a read operation, storing this detected delay value, and then using the pre-stored locking delay to generate a retimed timing signal during subsequent write operations. This eliminates the need for real-time delay detection during critical data transmission, thereby maintaining high speed while improving reliability through pre-calibrated timing synchronization.
Solution Approach 2:
The interface chip serves as an intermediary between the memory controller and the semiconductor memory chips. It detects timing skew, generates compensated timing signals with proper delay, and retimes data signals accordingly. This intermediary function isolates the timing synchronization problem from the main data transmission path, allowing high-speed operation while maintaining reliability through centralized timing management.
2Quantity of substance
If the number of overlapped semiconductor chips is increased to achieve higher capacity, then the capacity is improved, but the resistance component increases which reduces channel toggle speed and increases skew
Solution Approach 1:
The interface chip acts as an intermediary that manages timing synchronization for multiple overlapped semiconductor memory chips. It detects locking delays from timing signals and generates retimed signals that compensate for cumulative skew effects. This allows the system to scale capacity by adding more chips while maintaining proper timing synchronization and toggle speed through centralized delay compensation.
Solution Approach 2:
The system implements feedback by detecting the actual locking delay between timing signals during read operations, storing this measured delay information, and using it to adjust and generate appropriately delayed timing signals for write operations. This feedback mechanism ensures that timing signals remain synchronized even as the number of overlapped chips increases, thereby maintaining toggle speed and reducing skew.
3Productivity
If the speed of the storage device is increased using DDR method, then the speed is improved, but the skew increases which reduces reliability
Solution Approach 1:
The patent applies preliminary action by detecting and storing the locking delay between DQS and reference clock signals in advance during read operations. This pre-detected delay information is then used to generate properly retimed timing signals during high-speed write operations, eliminating the need for real-time delay calculation and ensuring accurate timing synchronization at DDR speeds, thereby maintaining reliability.
Solution Approach 2:
The interface chip serves as an intermediary that manages timing synchronization during high-speed DDR operations. It receives timing signals from the memory controller, detects locking delays, generates retimed timing signals with appropriate delay compensation, and outputs them to the semiconductor memory chips. This intermediary function isolates and manages skew effects, allowing high-speed operation while maintaining reliability through centralized timing control.
Data Source
AI summary
Provided herein may be a semiconductor memory device. The semiconductor memory device may include a memory unit configured to store the write data. The semiconductor memory device may include an interface chip configured to receive a first timing signal and a second timing signal, and configured to detect a locking delay from the first timing signal and generate a third timing signal from the second timing signal generated by delaying the first timing signal using the detected locking delay by at least two periods.