DRAM Memory Interface Translation for Signal Integrity
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As device scaling and chip-multi processor architectures advance, memory systems face challenges in achieving greater throughput, power consumption, and reliability due to signal integrity issues caused by increasing DRAM channel frequencies, which limit total memory capacity and introduce time delays in data bus utilization.
Innovation Solution
Implementing a wide internal data bus in DRAM modules operating at lower frequencies to support low-power, low-cost DRAM chips, while using memory interface translation techniques to maintain high-performance external data access speeds through a narrower external data bus, enabling the use of lower-performance DRAM chips for high-performance memory interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If DRAM channel frequencies are increased to provide higher throughput, then memory performance is improved, but signal integrity deteriorates and total memory capacity is limited
Solution Approach 1:
The patent segments the memory system into multiple independent memory channels, each operating at lower frequencies with better signal integrity. Instead of one high-frequency channel, multiple lower-frequency channels are used in parallel to achieve the same or higher aggregate throughput while maintaining reliable signaling on each individual channel.
2Quantity of substance
If more memory ranks or modules are added to increase total memory capacity, then memory capacity is improved, but signal integrity on the data bus deteriorates
Solution Approach 1:
The patent divides the memory system into multiple independent channels, each with its own data bus operating at lower frequencies. This segmentation allows more memory ranks to be distributed across multiple channels without overloading any single data bus, thereby maintaining signal integrity while increasing total memory capacity.
3Adaptability or versatility
If rank switching is performed at high DRAM clock frequencies, then memory access flexibility is improved, but idle cycles are introduced on data buses causing time delays
Solution Approach 1:
The patent uses lower DRAM clock frequencies that are synchronized with the external data bus timing, eliminating the need for rank switching at inconvenient moments. The periodic action of the lower-frequency clock allows memory operations to be completed within the available time slots without introducing idle cycles on the data bus.
4Use of energy by moving object
If low-power, low-frequency DRAM chips are used to reduce power consumption and cost, then power consumption and cost are improved, but external data access speed deteriorates
Solution Approach 1:
The patent combines multiple low-speed memory channels into a single high-speed external interface. Each individual DRAM chip operates at low frequency and low power, but by merging the output of multiple channels through a memory interface translator, the aggregate data transfer rate matches high-speed external bus requirements, achieving both low power consumption and high external access speed.
Solution Approach 2:
The patent introduces a memory interface translator as an intermediary component between the low-frequency DRAM chips and the high-speed external bus. This translator aggregates data from multiple low-speed channels and presents it to the external interface at the required high speed, allowing low-power memory chips to communicate at high speeds without directly operating at high frequencies.
Data Source
AI summary
A disclosed example method involves performing simultaneous data accesses on at least first and second independently selectable logical sub-ranks to access first data via a wide internal data bus in a memory device. The memory device includes a translation buffer chip, memory chips in independently selectable logical sub-ranks, a narrow external data bus to connect the translation buffer chip to a memory controller, and the wide internal data bus between the translation buffer chip and the memory chips. A data access is performed on only the first independently selectable logical sub-rank to access second data via the wide internal data bus. The example method also involves locating a first portion of the first data, a second portion of the first data, and the second data on the narrow external data bus during separate data transfers.