Memory Interface At-Speed Testing via Write-Thru Pipeline
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Solution Overview
Problem
Current methods for testing memory interfaces, particularly at-speed testing, face challenges in accurately detecting subtle delay faults and are costly in terms of silicon area, with existing scan tests and Built-In Self-Test (BIST) methods being inadequate for wide data buses and prone to missing faults.
Innovation Solution
The proposed solution involves a 'write-thru' process where two data words are written to and read from memory locations in fast succession, allowing the memory to act as a pipeline between input and output functional logic, reducing the number of at-speed clock cycles and power fluctuations, and enabling testing of multi-port memories with asynchronous clocks without the need for a memory BIST circuit for small memories.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional scan tests and BIST methods are used for memory interface testing, then testing coverage can be achieved, but silicon area cost increases and subtle delay faults are missed
Solution Approach 1:
The patent extracts the testing function from traditional scan chains and BIST circuits, using the memory device itself as the test instrument. By writing test patterns to memory and reading back results, the memory interface is tested without requiring extensive external test circuitry, thus reducing silicon area while maintaining fault detection capability
Solution Approach 2:
The patent makes the memory device multi-functional by using it both as the device under test and as the test instrument. The same memory cells, address decoders, and data paths are used for both normal operation and testing, eliminating the need for separate dedicated test circuits and reducing overall silicon area
2Measurement precision
If memory acts as pipeline with fast write-read succession, then timing testing accuracy improves and power fluctuations reduce, but test sequence complexity increases
Solution Approach 1:
The patent uses periodic clock cycles to structure the test sequence, with alternating phases of writing test patterns and reading back results. This periodic structure simplifies control logic by using the existing clock signal to synchronize test operations, making the sequence manageable despite the fast write-read succession required for accurate timing measurement
Solution Approach 2:
The patent changes the timing parameters of memory operations by performing writes and reads in rapid succession within specific clock cycles. This parameter change enables accurate timing measurement of the memory interface while using the existing clock infrastructure to manage the complexity of the test sequence
3Reliability
If at-speed testing is performed with multiple clock cycles, then fault coverage improves, but power consumption increases
Solution Approach 1:
The patent applies partial action by performing at-speed testing only for the specific clock cycles necessary to capture critical timing paths, rather than maintaining high-speed operation for all clock cycles. This allows adequate fault coverage on critical paths while reducing overall power consumption during the test sequence
Data Source
AI summary
Methods for at-speed testing of a memory interface associated with an embedded memory comprise two write operations in succession, two read operations in succession, and a capture operation using scan cells. The write and read operations are performed during a single clock burst, two separate clock bursts in a clock signal, or two separate clock bursts in separate clock signals.