Non-Volatile Memory Programming Method Using Interference-Aware Verify Voltage
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Solution Overview
Problem
Non-volatile semiconductor memory devices face challenges in minimizing interference between memory cells, leading to reduced read margins and multi-bit errors due to threshold voltage shifts caused by coupling effects, oxide layer deterioration, and programming disturbances.
Innovation Solution
A programming method that adjusts the program-verify-voltage of a selected memory cell based on interfering cells, using a memory controller to quantify interference and generate appropriate verify voltages to compensate for coupling effects, thereby minimizing errors during programming operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If memory cells are programmed using conventional verify voltage methods, then programming speed is maintained, but interference between adjacent memory cells causes threshold voltage shifts and multi-bit errors
Solution Approach 1:
The patent applies preliminary action by determining the states of interfering memory cells before programming the selected memory cell. The controller identifies whether adjacent cells are in programmed or erased states and pre-calculates the appropriate verify voltage level to compensate for the interference that will occur during programming. This advance preparation allows the selected cell to be programmed accurately despite the presence of interfering cells.
Solution Approach 2:
The patent implements parameter changes by dynamically adjusting the verify voltage level based on the states of interfering memory cells. Instead of using a fixed verify voltage, the controller selects from multiple verify voltage levels (first verify voltage for interfering cells in programmed state, second verify voltage for interfering cells in erased state). This parameter adjustment compensates for the coupling effects and oxide layer deterioration caused by adjacent cells.
2Manufacturing precision
If verify voltage is adjusted to compensate for interference, then programming accuracy improves, but programming time increases due to additional verification steps
Solution Approach 1:
The patent reduces programming time by performing the determination of interfering cell states and verify voltage selection in advance, before the actual programming operation begins. This preliminary analysis allows the controller to have the optimal verify voltage ready, eliminating the need for iterative verification adjustments during the programming process itself.
Solution Approach 2:
The patent uses feedback by monitoring the states of interfering memory cells and using this information to select the appropriate verify voltage level. The controller continuously tracks the programming status of adjacent cells and adjusts the verify voltage accordingly, creating a closed-loop system that optimizes programming accuracy without requiring excessive verification iterations.
3Reliability
If multiple verify voltage levels are used to account for interfering cell states, then programming reliability improves, but device complexity increases
Solution Approach 1:
The patent applies universality by designing the memory controller to handle multiple verify voltage scenarios using a unified control framework. The same controller logic manages both first verify voltage (for programmed interfering cells) and second verify voltage (for erased interfering cells) operations, making the control system multi-functional rather than requiring separate dedicated circuits for each scenario.
Solution Approach 2:
The patent manages device complexity by implementing parameter changes through software or firmware control rather than hardware modifications. The controller dynamically adjusts verify voltage levels based on interfering cell states using programmable logic, allowing flexibility in handling different interference scenarios without adding complex physical circuitry to the memory device itself.
Data Source
AI summary
Provided are a non-volatile memory system and a programming method thereof. The programming method of the non-volatile memory system includes adjusting a program-verify-voltage of a selected memory cell referring to program data to be written in an interfering cell configured to provide interference for the selected memory cell and programming the selected memory cell depending on the adjusted program-verify-voltage.