Memory Interface Load Balancing via Interleaving Circuit
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Solution Overview
Problem
Commercially available memory interface load balancing solutions fail to fully exploit multiplied memory bandwidth, especially when processing-modules do not access the entire memory space, and are resource-intensive and time-consuming for non-power of 2 interleaving ranks, limiting real interleaving for every possible value of interleaving rank.
Innovation Solution
A system and method that determine an arbitrary integer number of connected memory devices and apply interleaving functions to map original processor addresses to memory cluster addresses, using a controller and interleaving circuit to split and concatenate address sections, incorporating division, modulo, and hash functions to achieve efficient load balancing across memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If address interleaving algorithm is applied using division and modulo operations, then memory bandwidth is increased through multiple memory interfaces, but hardware resource consumption and timing complexity increase significantly for non-power-of-2 interleaving ranks
Solution Approach 1:
The patent changes the mathematical approach from division and modulo operations to multiplication and addition operations. Specifically, it uses a multiplier to multiply the lower address bits by a pre-calculated constant (interleaving factor), then adds the upper address bits. This parameter transformation enables efficient hardware implementation for any interleaving rank value, not just power-of-2 values, resolving the contradiction between supporting arbitrary interleaving ranks and maintaining hardware efficiency.
Solution Approach 2:
The patent replaces the mechanical division and modulo operations with a purely arithmetic multiplication and addition system. By using a multiplier circuit instead of a divider circuit, and a adder circuit instead of a modulo operator, the system achieves the same address mapping function with significantly reduced hardware complexity and faster execution time, especially for non-power-of-2 interleaving ranks.
2Productivity
If address interleaving is implemented with fixed address interval access patterns, then mapping to same memory interface occurs, but memory bandwidth utilization becomes suboptimal
Solution Approach 1:
The patent introduces asymmetry in the address mapping function by using an odd interleaving factor (when interleaving rank is even) or a non-trivial multiplier constant. This asymmetric multiplication causes addresses with fixed intervals to map to different memory interfaces, breaking the periodic mapping pattern that occurs with simple division-based interleaving. The asymmetric transformation ensures better distribution of sequential accesses across multiple memory interfaces, improving bandwidth utilization.
3Adaptability or versatility
If division and modulo operations are used for address mapping, then arbitrary interleaving ranks are supported, but additional clock cycles and timing constraints are required
Solution Approach 1:
The patent performs preliminary calculation of the interleaving factor (multiplier constant) during system initialization or configuration, storing it in a lookup table or register. This pre-computed value is then reused for all subsequent address mapping operations, eliminating the need for repeated division and modulo calculations. The preliminary action of pre-calculating the multiplier enables fast, constant-time address mapping for any interleaving rank, resolving the time loss issue while maintaining arbitrary rank support.
Data Source
AI summary
A system and a method of balancing a load of access of at least one computing device to an arbitrary integer number of connected memory devices associated with a memory cluster address space, the method including: determining, by a controller, a number N corresponding to an arbitrary integer number of memory devices connected to a plurality of memory interfaces, wherein N is between 1 and the number of memory interfaces; receiving, by the controller, at least one data object, corresponding to an original processor address (OPA) from the at least one computing device; computing, by the controller, at least one interleaving function according to N; and mapping, by an interleaving circuit, the OPA to a memory cluster address (MCA), according to the at least one interleaving function, so that the data object is equally interleaved among the N connected devices.