Memory Interleaving for Asymmetric Channel Capacities
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Solution Overview
Problem
Conventional computing devices with multiple processors or cores face data transfer bottlenecks due to asymmetric memory capacities across memory channels, leading to reduced data transfer rates and complications in identifying supported functions and applications.
Innovation Solution
The implementation of a system that identifies virtual sectors of equal storage capacity across multiple channels and uses an interleaving function to distribute data accesses uniformly, allowing for optimized data transfer rates even with non-uniform memory capacities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory modules are deployed to achieve a desired system memory capacity that is not a multiple of the minimum storage capacity of available memory modules, then the total memory capacity requirement is met, but asymmetric memory capacities across memory channels result in reduced data transfer rates
Solution Approach 1:
The memory space is divided into multiple virtual sectors, each with equal storage capacity. This segmentation allows the memory controller to uniformly distribute data across channels with asymmetric physical capacities, enabling each channel to operate at its maximum data rate while maintaining uniform access patterns. The virtual sector concept divides the total memory space into N equal portions, where N corresponds to the number of channels, allowing each channel to receive data for one virtual sector at a time.
Solution Approach 2:
The patent introduces an intermediary layer (virtual sectors) between the physical memory channels with asymmetric capacities and the memory controller. This intermediary allows the controller to issue uniform interleaved addresses to all channels simultaneously, while the channels process data at their respective maximum rates. The virtual sector mapping acts as a mediator that translates uniform access patterns into channel-specific data distributions, resolving the bandwidth limitation caused by asymmetric capacities.
2Ease of manufacture
If conventional interleaving schemes are used with asymmetric memory capacities, then some memory space can be accessed in a non-interleaved manner, but this introduces complications for operating systems and applications to identify supported functions
Solution Approach 1:
The patent creates a universal virtual sector interface that works uniformly across all memory channels regardless of their asymmetric physical capacities. The virtual sector concept provides a common addressing scheme that enables all channels to participate in interleaved access patterns. This universal interface simplifies operating system and application memory management, as they can use standard interleaved addressing without needing to identify or handle non-interleaved portions of memory space.
3Productivity
If memory channels are configured with equal storage capacity, then uniform interleaving can be achieved at maximum data rate, but this prevents achieving desired system memory capacities that are not multiples of the minimum module capacity
Solution Approach 1:
The patent changes the parameter of memory addressing from physical channel-based addressing to virtual sector-based addressing. By introducing virtual sectors as an intermediate addressing level, the system can maintain uniform interleaved access patterns (parameter of access pattern) while accommodating varying physical capacities across channels (parameter of channel capacity). This parameter transformation allows the memory controller to issue uniform addresses that map to appropriate channels based on virtual sector boundaries, enabling both maximum data rates and flexible capacity configurations.
Data Source
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AI summary
Systems and methods for uniformly interleaving memory accesses across physical channels of a memory space with a non-uniform storage capacity across the physical channels are disclosed. An interleaver is arranged in communication with one or more processors and a system memory. The interleaver identifies locations in a memory space supported by the memory channels and is responsive to logic that defines virtual sectors having a desired storage capacity. The interleaver accesses the asymmetric storage capacity uniformly across the virtual sectors in response to requests to access the memory space.