Nonvolatile Memory Interleaving for Read Error Equalization
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Multi-level cell nonvolatile memory devices face reliability issues and increased read failure rates as the number of bits stored in a single memory cell increases, due to limited voltage windows and varying bit error rates across pages at the end of life, making it difficult to adjust verify-read voltages for equal reliability across all pages.
Innovation Solution
A nonvolatile memory device employing interleaving technology, where a first controller allocates 2N threshold voltage states to N-bit data, and a second controller sets increasing differences between adjacent states to equalize read errors, considering threshold voltage shifts and coupling effects, using gray coding and verify-read voltage adjustments to form optimal threshold voltage distributions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of bits stored in a single memory cell increases, then memory integration is improved, but reliability deteriorates and read failure rate increases
Solution Approach 1:
The patent applies local quality by making the threshold voltage distribution characteristics different across various pages. Specifically, different pages are assigned different verify-read voltages based on their local error characteristics, allowing each page to be optimized independently rather than using a uniform approach across all pages.
Solution Approach 2:
The patent implements dynamics by making the verify-read voltage adjustable and page-specific rather than fixed and uniform. The system dynamically selects appropriate verify-read voltages for different pages based on their threshold voltage distribution characteristics, enabling adaptive optimization of read reliability across the memory device.
2Reliability
If verify-read voltage is adjusted to equalize bit error rate across pages, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-characterizing the threshold voltage distribution of each page during manufacturing or initial operation. This pre-characterization data is stored and used to determine appropriate verify-read voltages for each page, avoiding the need for complex real-time adjustments during normal operation.
Solution Approach 2:
The system implements self-service by using the memory device's own threshold voltage distribution characteristics to automatically determine the optimal verify-read voltages for each page. The device characterizes itself and configures its read parameters based on its inherent properties, reducing the need for external complex control mechanisms.
3Ease of manufacture
If gray code is used for programming multi-level flash memory, then manufacturing is simplified, but read error rate increases due to exponential increase in read operations
Solution Approach 1:
The patent applies local quality by assigning different verify-read voltages to different pages based on their specific threshold voltage distributions. This allows each page to be read with optimized voltage parameters tailored to its local characteristics, compensating for the increased read complexity introduced by gray code programming.
Data Source
AI summary
A nonvolatile memory device using interleaving technology is provided. The nonvolatile memory device includes a first controller configured to allocate one of 2N threshold voltage states to N-bit data where N is 2 or a natural number greater than 2, a second controller configured to set a difference between adjacent threshold voltage states among the 2N threshold voltage states so that the difference increases as a threshold voltage increases, and a programming unit configured to form a threshold voltage distribution state corresponding to the allocated threshold voltage state and to program the N-bit data to a multi-level cell. The second controller controls the difference between the adjacent threshold voltage states to equalize the number of read errors for all intersections among the 2N threshold voltage states at the end of life.