Memory Interleaving for Host Coprocessor Access
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Solution Overview
Problem
In computing systems, the inefficient use of memory arises when additional processors or peripherals, capable of limited parallel access to memory die, share memory with a host processor that can access multiple memory die in parallel, leading to suboptimal memory utilization.
Innovation Solution
A computing system architecture that employs a coprocessor and processor to store data blocks in an interleaved pattern across multiple memory devices, allowing the host processor to store data in one memory device while the coprocessor accesses it, and using fine-grained or coarse-grained interleaving patterns to optimize access based on the primary user of the data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If separate independent memory dies are used for additional processors or peripherals, then each processor can access memory independently, but memory utilization efficiency deteriorates
Solution Approach 1:
The patent implements a unified memory system where a single memory die is shared by multiple processors and peripherals through an interconnect network. This allows the memory resource to serve multiple functions and users simultaneously, improving overall utilization efficiency while maintaining independent access capabilities for each processor through logical address mapping and arbitration mechanisms.
2Speed
If multiple memory die are accessed in parallel by host processor, then data read/write speed increases, but memory configuration complexity increases
Solution Approach 1:
The patent divides the memory system into multiple independent memory dies, each capable of handling access requests independently. The host processor can access multiple memory dies in parallel through an interconnect network, achieving high data transfer speeds. The segmentation allows each memory die to be managed separately, reducing the complexity of controlling the entire memory system as a single unit.
Solution Approach 2:
The patent introduces an interconnect network as an intermediary between the host processor and multiple memory dies. This intermediary manages the parallel access requests, routing data flows efficiently while simplifying the control logic for each individual memory die. The interconnect handles address translation, arbitration, and data routing, reducing the overall system complexity.
3Ease of operation
If additional processors use separate independent memory dies, then access capability is maintained, but system performance deteriorates
Solution Approach 1:
The patent merges multiple memory resources into a unified memory system that is shared by the host processor and coprocessor. Instead of using separate independent memory dies, the system combines memory resources and manages them through a centralized controller that can allocate access dynamically. This merging improves system performance by better utilizing available memory bandwidth and reducing redundancy, while the controller ensures that both processors maintain their access capabilities.
Data Source
AI summary
A system and method are disclosed for managing memory interleaving patterns in a system with multiple memory devices. The system includes a processor configured to access multiple memory devices. The method includes receiving a first plurality of data blocks, and then storing the first plurality of data blocks using an interleaving pattern in which successive blocks of the first plurality of data blocks are stored in each of the memory devices. The method also includes receiving a second plurality of data blocks, and then storing successive blocks of the second plurality of data blocks in a first memory device of the multiple memory devices.