Memory Interleaving Device Reorders Messages to Prevent Deadlock
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
In a System on Chip (SoC), it is challenging to efficiently interface and manage memory requests from different intellectual properties (IPs) due to the requirement for in-order access, which can lead to deadlock situations and limit memory parallelism, making it difficult to maximize performance without redesigning existing IPs.
Innovation Solution
A memory interleaving device with a crossbar switch and reorder buffers is implemented to manage requests and data transmission between master and slave IPs, ensuring that requests are reordered and transmitted in the correct order, preventing deadlock and maximizing memory parallelism without requiring redesign of existing IPs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory requests are transmitted in parallel to multiple slave IPs, then memory parallelism is improved, but deadlock situations occur due to out-of-order message delivery
Solution Approach 1:
The patent introduces a message reorder buffer as an intermediary component between the crossbar switch and the master IP. This reorder buffer receives out-of-order messages from the crossbar switch, buffers them temporarily, and outputs them in the correct order to the master IP. By inserting this intermediary, the system can maintain high parallelism through the crossbar switch while ensuring reliable in-order delivery to the master IP, thus resolving the deadlock issue without sacrificing productivity.
2Reliability
If in-order access is enforced to prevent deadlock, then reliability is improved, but memory parallelism is limited
Solution Approach 1:
The patent segments the memory access path into two independent parts: (1) the crossbar switch that handles parallel request routing to multiple slave IPs, and (2) the message reorder buffer that ensures in-order message delivery to the master IP. This segmentation allows the parallel processing function to operate independently in the crossbar switch while the ordering function is handled separately by the reorder buffer, thereby achieving both high memory parallelism and reliable in-order access.
3Productivity
If existing IPs are redesigned to handle out-of-order access, then memory parallelism is improved, but device complexity increases
Solution Approach 1:
Instead of redesigning existing master or slave IPs to handle out-of-order access, the patent introduces a message reorder buffer as an intermediary component that transparently handles the reordering task. This approach maintains the simplicity of existing IP designs while enabling high memory parallelism through the crossbar switch. The reorder buffer absorbs the complexity of managing out-of-order messages, allowing existing IPs to remain unchanged and reducing overall device complexity.
Data Source
AI summary
A memory interleaving device includes a slave interface, a master interface, and a crossbar switch. The slave interface is connected with a master intellectual property through an on-chip network. The master interface is connected with a slave intellectual property. The crossbar switch connects the slave interface with the master interface. The memory interleaving device transmits requests from the master intellectual property to the slave intellectual property, receives data or responses respectively corresponding to the requests from the slave intellectual property, and transmits the data or responses to the master intellectual property in an order in which the requests are received.