Memory Interleaving for Unequal Channel Capacities
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Solution Overview
Problem
When memory channels in a system have unequal capacities, using the same interleaving window and algorithm can lead to uneven access distribution, resulting in performance differences across address spaces, while employing different windows and algorithms exacerbates this issue by enabling different fetch performance.
Innovation Solution
A memory interleaving method that divides access capacity into partial capacities based on configuration information and maps these capacities to memory channels using a configuration mapping table, ensuring balanced access across channels to maintain consistent fetch performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the same interleaving window and algorithm are used for all memory channels, then the interleaving process is simple and unified, but access becomes concentrated in specific memory channels when capacities are unequal, leaving other channels idle
Solution Approach 1:
The patent applies local quality by configuring different interleaving parameters (window size, stride, offset) for different memory channels based on their specific capacities. Each memory channel receives customized interleaving configuration information from the configuration module, allowing the system to optimize access distribution locally for each channel rather than applying a uniform global configuration. This resolves the contradiction by maintaining simple unified control logic while achieving differentiated local optimization.
2Productivity
If different interleaving windows and algorithms are used for different memory channels, then access distribution can be optimized for each channel, but different fetch performance is enabled across address spaces, creating performance disparities
Solution Approach 1:
The patent employs parameter changes by dynamically adjusting interleaving configuration parameters (window size, stride, offset) based on the detected capacities of different memory channels. The configuration module calculates optimal parameters for each channel and applies them through the same interleaving algorithm framework, achieving differentiated optimization without fundamentally changing the algorithm structure. This maintains fetch performance consistency while optimizing access efficiency for each channel's specific capacity.
3Adaptability or versatility
If memory channels have unequal capacities, then system flexibility and adaptability are improved, but uneven access distribution occurs when using uniform interleaving, resulting in idle channels and performance loss
Solution Approach 1:
The patent applies dynamics by making the interleaving configuration adaptive and dynamic rather than static. The configuration module detects the actual capacities of memory channels at runtime and dynamically generates appropriate configuration information for each channel. This dynamic adaptation allows the system to efficiently utilize memory channels with unequal capacities, preventing idle channels and maintaining high productivity while preserving system flexibility.
Data Source
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AI summary
Embodiments of this application disclose a memory interleaving method and an apparatus, relate to the computer field, and resolve a problem that fetch performance of different address spaces is different when two interleaving windows and two interleaving algorithms are used to interleave access. A specific solution is: dividing an access capacity into P partial access capacities based on N pieces of configuration information, where the P partial access capacities have a same size, the N pieces of configuration information are configuration information of N memory channels, one piece of configuration information corresponds to one memory channel, the configuration information is used to indicate a quantity of capacities mapped to the memory channel, and two capacities are mapped to at least one of the N memory channels, where N represents a total quantity of memory channels, and N is an integer greater than or equal to 2; and mapping the P partial access capacities to the N memory channels according to a configuration mapping table, where the configuration mapping table is used to indicate a mapping relationship between the capacity and the memory channel. The embodiments of this application are used in a memory interleaving process.