Memory Systems Internal Channel Data Routing

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Solution Overview

Problem

Existing data processing systems face challenges in efficiently transferring data between multiple memory systems and a host, particularly when read operations are intensive on specific memory systems, leading to bottlenecks and reduced data availability to the host.

Innovation Solution

A data processing system is designed with multiple nonvolatile memory devices connected through external channels and an internal channel, allowing the host to control data transfer modes such as sole or simultaneous use of external channels, enabling data sharing between memory systems to alleviate bottlenecks and ensure efficient data delivery to the host.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If data is transferred only through external channels from a single memory system, then the host can access data directly, but the system experiences bottlenecks during intensive read requests on specific memory systems

Engineering Contradiction:
Improvedata transfer efficiencyVSAvoiddata availability to host
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The patent introduces an internal channel as an intermediary communication path between multiple memory systems. When one memory system experiences intensive read requests, it can transfer data through the internal channel to another memory system, which then delivers the data to the host through its external channel. This mediator approach resolves the bottleneck by distributing the data delivery load across multiple external channels while maintaining reliable data availability to the host.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Reliability

If multiple memory systems are connected through external channels to the host, then data availability improves, but system complexity increases due to multiple connection paths

Engineering Contradiction:
Improvedata availabilityVSAvoidconnection structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent segments the communication paths into two distinct types: external channels connecting memory systems to the host, and internal channels connecting memory systems to each other. This segmentation allows the system to maintain multiple connection paths for improved reliability while organizing the complexity into manageable, standardized interface types. Each memory system has one external channel for host communication and internal channel interfaces for peer-to-peer communication.

Inventive Principle:
Principle #1Segmentation

3Device complexity

If a single external channel is used for data transfer, then the connection structure is simple, but the system experiences bottlenecks during intensive read operations

Engineering Contradiction:
Improveconnection structureVSAvoiddata transfer speed
Core Design Contradiction:
Device complexityVSProductivity

Solution Approach 1:

The patent adds another dimension to the communication architecture by introducing internal channels that operate in parallel to the external channels. Instead of simply increasing the number of external channels (one dimension), the system creates a two-dimensional communication matrix where data can flow from any memory system through internal channels to any other memory system, and then to the host through external channels. This dimensional expansion enables simultaneous data transfers through multiple paths, dramatically improving data transfer speed without proportionally increasing external connection complexity.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Data Source

PatentUS11016914B2Data processing system including memory systems coupled through internal channel
Publication Date: 2021.05.25 MIMIRIP LLC
  • US11016914B2 patent drawing
  • US11016914B2 patent drawing
  • US11016914B2 patent drawing

AI summary

A data processing system comprising: a first memory system coupled to a host through a first external channel, a second memory system coupled to the host through a second external channel, and an internal channel suitable for coupling the first and second memory systems with each other, the host, when read-requesting first and second data to the first memory system, transfers a first external channel control information for selecting sole use of the first external channel or simultaneous use of the first and second external channels, to the first and second memory systems, the first memory system, when the first external channel control information indicates simultaneous use, the first memory system outputs the first data through the first external channel and outputs the second data through the internal channel, and the second memory system outputs the second data inputted through the internal channel, through the second external channel.