Semiconductor Memory Internal Data Transfer via JEDEC Interface
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Solution Overview
Problem
Existing semiconductor memory systems, particularly those conforming to the JEDEC standard for DDRx-SDRAM and LPDDRx-SDRAM, face inefficiencies in data transfer as they require data to pass through a bus outside the memory device, leading to high power consumption and prolonged processing times, especially in high-frequency operations.
Innovation Solution
The implementation of a semiconductor memory device and control device with an internal data bus connecting banks via sense amplifiers, allowing for data transfer between memory cells within the device without using the external bus by employing additional transfer commands and signal values not defined in the JEDEC standard, enabling data to be written or read between memory cells without external bus occupation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transfer is performed through the external bus in conventional memory systems, then the interface between processor and memory can be used for data transfer operations, but power consumption increases and processing time is prolonged
Solution Approach 1:
The memory device is divided into multiple banks, each capable of independent operation. The segmentation allows data transfer to occur within specific banks using internal bit lines and sense amplifiers, bypassing the need for external bus communication and reducing power consumption while maintaining transfer speed.
Solution Approach 2:
Sense amplifiers serve as intermediaries between memory cells and bit lines. These amplifiers enable direct data transfer between banks by amplifying signals locally within the memory device, eliminating the need for data to traverse the external bus and thereby reducing power consumption and transfer time.
2Adaptability or versatility
If data transfer is performed through the external bus, then standard JEDEC interface can be used, but the interface is occupied for data transfer and cannot perform other operations simultaneously
Solution Approach 1:
By segmenting the memory into independent banks with dedicated internal bit lines, the system enables parallel operations within different banks. One bank can perform data transfer while another bank handles read/write operations, allowing the interface to remain available for other tasks and reducing overall processing time.
Solution Approach 2:
The patent implements preliminary action by pre-charging bit lines and preparing sense amplifiers within banks before data transfer operations. This allows data to be transferred between banks using internal resources without occupying the external interface, enabling the interface to be used for other operations simultaneously and reducing processing time.
3Productivity
If additional transfer commands are implemented beyond JEDEC standard, then internal data transfer capability is enabled, but device complexity increases
Solution Approach 1:
The sense amplifiers and bit lines are designed to serve multiple functions: they can be used for standard read/write operations and simultaneously for internal data transfer between banks. This multi-functionality enables efficient internal data transfer without requiring separate dedicated circuits, thereby limiting the increase in device complexity while improving productivity.
Solution Approach 2:
The patent utilizes parameter changes by modifying the operational state of existing memory components. By changing the activation state of sense amplifiers and the voltage levels on bit lines, the system enables internal data transfer functionality using existing hardware, avoiding the need for additional complex control circuits and minimizing device complexity increase.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces power consumption and processing time by allowing internal data transfer within the memory device, enhancing efficiency and performance, especially in high-frequency operations, while maintaining compatibility with the JEDEC standard.
Implementation Method 1
A sense amplifier, connected to the complementary bit line pair, amplifies the slight potential difference for setting a bit-line potential level to a power supply level and to set another bit-line potential level to a ground level
Data Source
AI summary
A control device of the invention for a semiconductor memory device comprising an interface conforming to JEDEC standard of DDRx-SDRAM or LPDDRx-SDRAM, comprises banks, a read/write control circuit, and a transfer control circuit. Each bank comprises subarrays. Each subarray comprises memory cells arranged along bit lines and word lines. The read/write control circuit controls reading of data from and writing of data to the semiconductor memory device. The transfer control circuit controls data transfer inside the semiconductor memory device and sets to enable an additional transfer command not specified in the JEDEC standard and a transfer command for writing data, read from a transfer source memory cell, to a transfer destination memory cell without passing outside the semiconductor memory device by transmitting a first signal value not used in the JEDEC standard to the semiconductor memory device via at least one signal line of the interface.