Semiconductor Memory Internal Data Transmission via Sense Amplifiers
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Solution Overview
Problem
The increasing need for efficient data transmission during memory copy operations in semiconductor memory devices, driven by the growing use of multiple operating systems, is not adequately addressed by existing technologies, leading to inefficiencies in data traffic management.
Innovation Solution
A semiconductor memory device with a memory controller, pair of data lines, and multiple memory banks that utilize internal control signals, address signals, and sense amplifiers to efficiently read and write data between source and target addresses using global and internal data I/O lines, enabling internal data transmission without external resources.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data is transmitted externally during memory copy operations, then data can be transferred between memory regions, but data traffic inefficiency increases and external system intervention is required
Solution Approach 1:
The patent extracts the data transmission function from the external system by introducing dedicated internal data transmission lines (IDTL0, IDTL1) that operate independently from external data lines. This allows memory copy operations to be performed internally without involving external systems, thereby improving data transmission efficiency and reducing data traffic inefficiency on external buses.
Solution Approach 2:
The patent introduces sense amplifiers as intermediary components that enable direct data transfer between memory banks through internal data transmission lines. The sense amplifiers act as mediators that read data from source memory banks and write it to target memory banks without external intervention, thus improving productivity while reducing the burden on external data traffic.
2Productivity
If internal data transmission lines are added, then internal data transfer efficiency improves, but device complexity increases
Solution Approach 1:
The patent merges the functions of data transmission and sense amplification by using the same sense amplifier circuits to serve both external data I/O and internal data transmission. The sense amplifiers are configured to selectively connect to either external data lines or internal data transmission lines based on operation mode, thereby improving internal data transfer efficiency without proportionally increasing device complexity.
Solution Approach 2:
The patent implements multi-functionality in the sense amplifier circuits that can operate in multiple modes: external data I/O mode and internal data transmission mode. This universal design allows the same hardware components to serve dual purposes, improving internal data transfer efficiency while minimizing the increase in device complexity through resource sharing.
3Speed
If sense amplifiers are used for internal data transmission, then data read and write operations are accelerated, but manufacturing complexity increases
Solution Approach 1:
The patent uses sense amplifiers that are already present in conventional memory structures to perform internal data transmission. By copying the existing sense amplifier design and configuring it to support internal data transmission in addition to external I/O, the patent accelerates data read and write operations without significantly increasing manufacturing complexity, as the basic sense amplifier circuitry is replicated rather than redesigned.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables efficient data transmission during memory copy operations, reducing data traffic inefficiencies and allowing for internal data transfer without external system intervention, thereby enhancing the functionality of semiconductor memory devices in multi-operating system environments.
Implementation Method 1
The NMOS sense amplifier may sense a high-level signal of the bit line or the inverted bit line and amplify a signal of an inverted local data input/output (I/O) line or a local data I/O line to a low level
Implementation Method 2
The PMOS sense amplifier may sense a low-level signal of the bit line or the inverted bit line and amplify the signal of the inverted local data input/output line or the local data I/O line to a high level
Implementation Method 3
The local sense amplification unit may sense the high-level signal of the local data I/O line or the inverted local data I/O line and amplify a signal of an inverted global data I/O line or a global data I/O line to a low level in response to the internal read signal
Data Source
AI summary
In a semiconductor memory device and an internal data transmission method thereof, the device includes a memory controller, a pair of data lines, and a plurality of memory banks. During an internal data transmission operation, the memory controller externally receives and stores a source address and a target address in response to an externally applied command and outputs an internal control signal and an internal address signal using the source address and the target address. The internal control signal includes an internal write signal and an internal read signal. Transmission data is transmitted on the pair of data lines during the internal data transmission operation. The plurality of memory banks read the transmission data stored in a region corresponding to the source address in response to the internal read signal, transmit the transmission data on the pair of data lines, and write the transmission data transmitted on the pair of data lines in response to the internal write signal. During the internal data transmission operation, the transmission data is transmitted from the region corresponding to the source address to a region corresponding to the target address, and is not output external to the semiconductor memory device.