Semiconductor Memory Internal Processing Mode
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Solution Overview
Problem
Semiconductor memory devices face increased costs and performance limitations due to the need for separate interfaces and burdens on host arithmetic operations, especially when performing internal processing tasks.
Innovation Solution
A semiconductor memory device with an internal processor that operates in both normal and internal processing modes, using a memory cell array to store and process information, allowing for reduced interface variation and improved performance by performing internal processing operations based on stored processing information.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a separate interface is added for internal processing operations, then the functionality and versatility of the memory device is improved, but the device complexity and manufacturing cost increase
Solution Approach 1:
The patent makes the existing interface circuitry universal by enabling it to handle both normal memory operations and internal processing operations through mode indicators. The same data input circuit receives both data signals and processing information, and the same memory cell array serves both as data storage and as storage for processing information, eliminating the need for separate dedicated interfaces.
Solution Approach 2:
The patent merges the normal operation interface and the internal processing interface into a single unified interface. The data input circuit, memory cell array, and control logic are combined to serve dual purposes, reducing device complexity while maintaining both functionalities through mode-based operation selection.
2Adaptability or versatility
If processing information is stored in a separate memory region, then the internal processing capability is improved, but the device complexity and cost increase
Solution Approach 1:
The memory cell array is designed to be universal, serving both as data storage for normal operations and as storage for processing information for internal processing operations. The same memory cells are dynamically allocated for different purposes based on the mode indicator, eliminating the need for separate dedicated memory regions.
Solution Approach 2:
The patent implements dynamic allocation of memory cell regions through mode indicators. The first memory cell region and second memory cell region are not fixed but are dynamically designated based on whether the device is in normal mode or internal processing mode, allowing the same physical memory to serve multiple functions without requiring separate dedicated regions.
3Productivity
If the memory device performs internal processing operations, then the productivity and performance are improved, but the interface complexity increases
Solution Approach 1:
The interface circuitry is designed to be universal, handling both data signals and processing information through the same data input circuit. The mode indicator enables the interface to dynamically switch between receiving data for normal operations and receiving processing information for internal processing, maintaining high performance while minimizing interface complexity.
Data Source
AI summary
An operation method of a semiconductor memory device including a memory cell array and an internal processor configured to perform an internal processing operation includes receiving at the memory device a first mode indicator that indicates whether the memory device should operate in a processor mode or in a normal mode, receiving at the memory device processing information for the memory device, when the first mode indicator indicates that the memory device should operate in the processor mode, storing the processing information in a first memory cell region of the memory cell array, using the stored processing information to perform internal processing by the internal processor, and storing a result of the internal processing in the memory cell array.